- Asa-dev - op-lists.linaro.org

by Marcin Juszkiewicz

ASA-dev mailing list was created years ago to discuss SBSA stuff. For quite a while it was the main place for discussion. In meantime we had team members coming and going away. Then we moved to upstream MLs. Nowadays the only thing asa-dev is doing is sending me moderation requests to reject spam mails. Therefore I opened a ticket to retire this mailing list. We will continue discussing SBSA stuff on EDK2/QEMU/etc mailing lists.

5 months, 1 week

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[RFC PATCH edk2-platforms v3 0/1] add basic support for CXL on sbsa-ref

by Yuquan Wang

v2 -> v3: - PCDs values of pio, mmio32, mmio64 & ecam space for the independent cxl host - CXL Bus range: 0x00 ~ 0xff - Mcfg ecam structure for cxl - Iort RC node for cxl RFC because - Many contents are ported from Jonathan' patch on qemu virt design - Bring plenty of PCDs values - Less experience and not particularly confident in ACPI area This series leverages Jonathan's patches[1] to add acpi0016 & acpi0017 objects into the previous DSDT table of sbsa-ref. Since my latest acpi0016 implementation model on qemu side is a new host bridge qemu object rather than pxb-cxl, the cxl host(Segment 0001) would have its own ECAM sapce. Meanwhile, this adds exclusive pio, mmio32 & mmio64 space for cxl host. As sbsa-ref cxl host has its own ecam space, this defines the bus range of cxl host from 0x0 to 0xff. Therefore, this adds relevant BASE_ADDRESS_ALLOCATION_STRUCTURE for cxl in Mcfg. And to enable msi of cxl components, this add a new RC node in Iort. Based on the new CEDT definitions patch on edk2[2], this series adds a static Cedt.aslc to support the [SBSA_CXL_CHBCR] & [SBSA_CXL_FIXED_WINDOW] space on sbsa-ref. Link: [1]: https://lore.kernel.org/linux-cxl/20220616141950.23374-2-Jonathan.Cameron@h… [2]: https://edk2.groups.io/g/devel/topic/rfc_edk2_patch_v3_0_1/109403423# Below are the new result of acpi tables (the DSDT contents could see the patch itself): 1) MCFG [000h 0000 004h] Signature : "MCFG" [Memory Mapped Configuration Table] [004h 0004 004h] Table Length : 0000004C [008h 0008 001h] Revision : 01 [009h 0009 001h] Checksum : 5A [00Ah 0010 006h] Oem ID : "LINARO" [010h 0016 008h] Oem Table ID : "SBSAQEMU" [018h 0024 004h] Oem Revision : 20240625 [01Ch 0028 004h] Asl Compiler ID : "LNRO" [020h 0032 004h] Asl Compiler Revision : 00000001 [024h 0036 008h] Reserved : 0000000000000000 [02Ch 0044 008h] Base Address : 00000000F0000000 [034h 0052 002h] Segment Group Number : 0000 [036h 0054 001h] Start Bus Number : 00 [037h 0055 001h] End Bus Number : FF [038h 0056 004h] Reserved : 00000000 [03Ch 0060 008h] Base Address : 0000000068140000 [044h 0068 002h] Segment Group Number : 0001 [046h 0070 001h] Start Bus Number : 00 [047h 0071 001h] End Bus Number : FF [048h 0072 004h] Reserved : 00000000 2) IORT [000h 0000 004h] Signature : "IORT" [IO Remapping Table] [004h 0004 004h] Table Length : 00000118 [008h 0008 001h] Revision : 06 [009h 0009 001h] Checksum : D3 [00Ah 0010 006h] Oem ID : "LINARO" [010h 0016 008h] Oem Table ID : "SBSAQEMU" [018h 0024 004h] Oem Revision : 20240625 [01Ch 0028 004h] Asl Compiler ID : "LNRO" [020h 0032 004h] Asl Compiler Revision : 00000001 [024h 0036 004h] Node Count : 00000004 [028h 0040 004h] Node Offset : 00000030 [02Ch 0044 004h] Reserved : 00000000 [030h 0048 001h] Type : 00 [031h 0049 002h] Length : 0018 [033h 0051 001h] Revision : 00 [034h 0052 004h] Identifier : 00000000 [038h 0056 004h] Mapping Count : 00000000 [03Ch 0060 004h] Mapping Offset : 00000000 [040h 0064 004h] ItsCount : 00000001 [044h 0068 004h] Identifiers : 00000000 [048h 0072 001h] Type : 04 [049h 0073 002h] Length : 0058 [04Bh 0075 001h] Revision : 05 [04Ch 0076 004h] Identifier : 00000000 [050h 0080 004h] Mapping Count : 00000001 [054h 0084 004h] Mapping Offset : 00000044 [058h 0088 008h] Base Address : 0000000060050000 [060h 0096 004h] Flags (decoded below) : 00000001 COHACC Override : 1 HTTU Override : 0 Proximity Domain Valid : 0 DeviceID Valid : 0 [064h 0100 004h] Reserved : 00000000 [068h 0104 008h] VATOS Address : 0000000000000000 [070h 0112 004h] Model : 00000000 [074h 0116 004h] Event GSIV : 0000004A [078h 0120 004h] PRI GSIV : 0000004B [07Ch 0124 004h] GERR GSIV : 0000004D [080h 0128 004h] Sync GSIV : 0000004C [084h 0132 004h] Proximity Domain : 00000000 [088h 0136 004h] Device ID Mapping Index : 00000001 [08Ch 0140 004h] Input base : 00000000 [090h 0144 004h] ID Count : 0000FFFF [094h 0148 004h] Output Base : 00000000 [098h 0152 004h] Output Reference : 00000030 [09Ch 0156 004h] Flags (decoded below) : 00000000 Single Mapping : 0 [0A0h 0160 001h] Type : 02 [0A1h 0161 002h] Length : 003C [0A3h 0163 001h] Revision : 00 [0A4h 0164 004h] Identifier : 00000000 [0A8h 0168 004h] Mapping Count : 00000001 [0ACh 0172 004h] Mapping Offset : 00000028 [0B0h 0176 008h] Memory Properties : [IORT Memory Access Properties] [0B0h 0176 004h] Cache Coherency : 00000001 [0B4h 0180 001h] Hints (decoded below) : 00 Transient : 0 Write Allocate : 0 Read Allocate : 0 Override : 0 [0B5h 0181 002h] Reserved : 0000 [0B7h 0183 001h] Memory Flags (decoded below) : 01 Coherency : 1 Device Attribute : 0 Ensured Coherency of Accesses : 0 [0B8h 0184 004h] ATS Attribute : 00000000 [0BCh 0188 004h] PCI Segment Number : 00000000 [0C0h 0192 001h] Memory Size Limit : 00 [0C1h 0193 002h] PASID Capabilities : 0000 [0C3h 0195 001h] Reserved : 00 [0C8h 0200 004h] Input base : 00000000 [0CCh 0204 004h] ID Count : 0000FFFF [0D0h 0208 004h] Output Base : 00000000 [0D4h 0212 004h] Output Reference : 00000048 [0D8h 0216 004h] Flags (decoded below) : 00000000 Single Mapping : 0 [0DCh 0220 001h] Type : 02 [0DDh 0221 002h] Length : 003C [0DFh 0223 001h] Revision : 00 [0E0h 0224 004h] Identifier : 00000001 [0E4h 0228 004h] Mapping Count : 00000001 [0E8h 0232 004h] Mapping Offset : 00000028 [0ECh 0236 008h] Memory Properties : [IORT Memory Access Properties] [0ECh 0236 004h] Cache Coherency : 00000001 [0F0h 0240 001h] Hints (decoded below) : 00 Transient : 0 Write Allocate : 0 Read Allocate : 0 Override : 0 [0F1h 0241 002h] Reserved : 0000 [0F3h 0243 001h] Memory Flags (decoded below) : 01 Coherency : 1 Device Attribute : 0 Ensured Coherency of Accesses : 0 [0F4h 0244 004h] ATS Attribute : 00000000 [0F8h 0248 004h] PCI Segment Number : 00000001 [0FCh 0252 001h] Memory Size Limit : 00 [0FDh 0253 002h] PASID Capabilities : 0000 [0FFh 0255 001h] Reserved : 00 [104h 0260 004h] Input base : 00000000 [108h 0264 004h] ID Count : 0000FFFF [10Ch 0268 004h] Output Base : 00010000 [110h 0272 004h] Output Reference : 00000030 [114h 0276 004h] Flags (decoded below) : 00000000 Single Mapping : 0 3) CEDT [000h 0000 004h] Signature : "CEDT" [CXL Early Discovery Table] [004h 0004 004h] Table Length : 000000A8 [008h 0008 001h] Revision : 01 [009h 0009 001h] Checksum : 50 [00Ah 0010 006h] Oem ID : "LINARO" [010h 0016 008h] Oem Table ID : "SBSAQEMU" [018h 0024 004h] Oem Revision : 20240625 [01Ch 0028 004h] Asl Compiler ID : "LNRO" [020h 0032 004h] Asl Compiler Revision : 00000001 [024h 0036 001h] Subtable Type : 00 [CXL Host Bridge Structure] [025h 0037 001h] Reserved : 00 [026h 0038 002h] Length : 0020 [028h 0040 004h] Associated host bridge : 00000001 [02Ch 0044 004h] Specification version : 00000001 [030h 0048 004h] Reserved : 00000000 [034h 0052 008h] Register base : 0000000060120000 [03Ch 0060 008h] Register length : 0000000000010000 [044h 0068 001h] Subtable Type : 01 [CXL Fixed Memory Window Structure] [045h 0069 001h] Reserved : 00 [046h 0070 002h] Length : 0064 [048h 0072 004h] Reserved : 00000000 [04Ch 0076 008h] Window base address : 00000A0000000000 [054h 0084 008h] Window size : 0000010000000000 [05Ch 0092 001h] Interleave Members : 00 [05Dh 0093 001h] Interleave Arithmetic : 00 [05Eh 0094 002h] Reserved : 0000 [060h 0096 004h] Granularity : 00000000 [064h 0100 002h] Restrictions : 000F [066h 0102 002h] QtgId : 0001 [068h 0104 004h] First Target : 00000001 Yuquan Wang (1): SbsaQemu: Support basic CXL enablement Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 21 ++ .../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 24 ++ Silicon/Qemu/SbsaQemu/AcpiTables/Cedt.aslc | 69 ++++ Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 327 ++++++++++++++++++ Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc | 9 +- .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 40 ++- Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 28 ++ 7 files changed, 515 insertions(+), 3 deletions(-) create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Cedt.aslc -- 2.34.1

5 months, 3 weeks

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[RFC PATCH v2 0/1] Sbsa-ref CXL Enablement

by Yuquan Wang

v1 -> v2: - provide CXL exclusive MMIO32 & MMIO64 space - hard coded two cxl root ports RFC because - Many contents are ported from Jonathan' patch on qemu virt design - Less experience and not particularly confident in sbsa-ref address space design so this might be stupidly broken in a way I've not considered. Currently the base CXL support for arm platforms is only on Jonathan's patches[1] which have not yet merged into upstream. SBSA-REF can be more like a real machine, thus the support of cxl could be meaningful. This series leverages Jonathan's patches[1] to design [SBSA_CXL_HOST] and [SBSA_CXL_FIXED_WINDOW] spaces for sbsa-ref layout. For [SBSA_CXL_HOST], since this creates a default pxb-cxl (bus_nr=0xc0) bridge with two cxl root ports on sbsa-ref, the new memory layout places 64K space for one hard coded cxl host bridge register regions in the sbsa-ref memmap. According to above design, for now only two cxl type3 devices could be added on the cxl host. With the 'create_pxb_cxl', users don't need to input '-device pxb-cxl' and '-device cxl-rp' parameters. In addition, this support indepentent mmio32(32M) & mmio64(1M) space which are enough for cxl components, because in this way the previous pcie mmio32/64 space would not be divided and affected. However, with the pxb-cxl-host, any cxl root ports and cxl endpoint devices would occupy the BDF number of the original pcie domain. Hence, the max available pcie devices on sbsa-ref would decrease, which seems to bring a series of trouble. I'm looking for some comments on the problems and suggestions on if there are better ways to do it. For [SBSA_CXL_FIXED_WINDOW], in order to provide CFMWs on sbsa-ref, this extends 1TB space from the hole above RAM Memory [SBSA_MEM] for CXL Fixed Memory Window. 0xA0000000000 is chosen as the base address of this space because of 3 reasons: 1) It is more suitable to choose a static address instead of that implementation in virt, since a dynamic address space layout of sbsa-ref is not appropriate for its original purpose as a reference platform. 2) The Hotplug Memory address range should in the range of maximum addressable range of sbsa-ref platform(0x10000000000-0x80ffffffffff). It is satisfied the requirements of memory hotplug in linux kernel. 3) The start pfn of CFMW should exceed the reserved_pfn_range for onlined numa node. Based on 'cxl_fmws_link_targets', this adds a new function 'sbsa_cxl_fmws_link_targets' for binding cfmws.target with the default pxb-cxl-bus on sbsa-ref. In addition, this also adds 'create_cxl_fixed_window_region' to support creating a static cfmw region on sbsa-ref, so users don't need to input '-M cxl-fmw' parameter. Thus, to run sbsa-ref with a cxl device could use: qemu-system-aarch64 \ -object memory-backend-file,id=mem2,mem-path=/tmp/mem2,size=256M,share=true \ -device cxl-type3,bus=cxl.0,volatile-memdev=mem2,id=cxl-mem1 \ By the way, since the matched firmware correspond to this patch would allocate pcie bus 0xc0 ~ 0xff to pxb-cxl-host, we should add "bus=pcie.0" when we want to plug some devices on the original pcie bus, for example: -device qemu-xhci,bus=pcie.0 \ or -device nvme,serial=deadbeef,bus=pcie.0,drive=hdd \ -drive file=../disk/hdd.qcow2,format=qcow2,id=hdd,if=none \ This series patches are here to hopefully some comments to guide me! Link: [1]: https://lore.kernel.org/linux-cxl/20220616141950.23374-1-Jonathan.Cameron@h… [2]: https://edk2.groups.io/g/devel/topic/rfc_edk2_patch_v3_0_1/109403423# [3]: https://edk2.groups.io/g/devel/topic/rfc_patch_edk2_platforms_v2/109403456 Yuquan Wang (1): hw/arm/sbsa-ref: Support CXL Host Bridge & CFMW docs/system/arm/sbsa.rst | 4 ++ hw/arm/sbsa-ref.c | 122 +++++++++++++++++++++++++++++++++++++- hw/cxl/cxl-host-stubs.c | 2 + hw/cxl/cxl-host.c | 2 +- include/hw/cxl/cxl_host.h | 2 + 5 files changed, 130 insertions(+), 2 deletions(-) -- 2.34.1

5 months, 3 weeks

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[RFC PATCH edk2-platforms v2 0/1] add basic support for CXL on sbsa-ref

by Yuquan Wang

v1 -> v2: - PCDs values about CXL exclusive MMIO32 & MMIO64 space - CXL Bus range: 0xc0 ~ 0xff - PCIE ecam space & Cxl ecam space - CEDT format RFC because - Many contents are ported from Jonathan' patch on qemu virt design - Bring plenty of PCDs values and modifying the original PCIE values - Less experience and not particularly confident in ACPI area This series leverages Jonathan's patches[1] to add acpi0016 & acpi0017 objects into the previous DSDT table of sbsa-ref. Since the acpi0016 implementation model on qemu side is the pxb-cxl, this cxl Bus would share ECAM sapce of PCIE Bus. Thus I divide some space from Pcie Ecam to support cxl-related values. To prevent breaking the original pcie mmio space, this adds exclusive mmio32 & mmio64 space for cxl host. This defines the pcie bus range of cxl host is 0xc0 ~ 0xff, since the pxb-cxl-host as well as cxl components on it would occupy the original pcie buses, the original pcie ecam space should divided some range for pxb-cxl-host. Based on the new CEDT definitions patch on edk2[2], this series adds a static Cedt.aslc to support the [SBSA_CXL_HOST] & [SBSA_CXL_FIXED_WINDOW] space on sbsa-ref. DSDT: Device (CXL0) { Name (_HID, "ACPI0016" /* Compute Express Link Host Bridge */) // _HID: Hardware ID Name (_CID, Package (0x02) // _CID: Compatible ID { EisaId ("PNP0A08") /* PCI Express Bus */, EisaId ("PNP0A03") /* PCI Bus */ }) Name (_BBN, 0xC0) // _BBN: BIOS Bus Number Name (_UID, One) // _UID: Unique ID Name (_STR, Unicode ("pxb Device")) // _STR: Description String Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_PRT, Package (0x80) // _PRT: PCI Routing Table { Package (0x04) { 0xFFFF, Zero, GSI0, Zero }, Package (0x04) { 0xFFFF, One, GSI1, Zero }, Package (0x04) { 0xFFFF, 0x02, GSI2, Zero }, Package (0x04) { 0xFFFF, 0x03, GSI3, Zero }, Package (0x04) { 0x0001FFFF, Zero, GSI1, Zero }, Package (0x04) { 0x0001FFFF, One, GSI2, Zero }, Package (0x04) { 0x0001FFFF, 0x02, GSI3, Zero }, Package (0x04) { 0x0001FFFF, 0x03, GSI0, Zero }, Package (0x04) { 0x0002FFFF, Zero, GSI2, Zero }, Package (0x04) { 0x0002FFFF, One, GSI3, Zero }, Package (0x04) { 0x0002FFFF, 0x02, GSI0, Zero }, Package (0x04) { 0x0002FFFF, 0x03, GSI1, Zero }, Package (0x04) { 0x0003FFFF, Zero, GSI3, Zero }, Package (0x04) { 0x0003FFFF, One, GSI0, Zero }, Package (0x04) { 0x0003FFFF, 0x02, GSI1, Zero }, Package (0x04) { 0x0003FFFF, 0x03, GSI2, Zero }, Package (0x04) { 0x0004FFFF, Zero, GSI0, Zero }, Package (0x04) { 0x0004FFFF, One, GSI1, Zero }, Package (0x04) { 0x0004FFFF, 0x02, GSI2, Zero }, Package (0x04) { 0x0004FFFF, 0x03, GSI3, Zero }, Package (0x04) { 0x0005FFFF, Zero, GSI1, Zero }, Package (0x04) { 0x0005FFFF, One, GSI2, Zero }, Package (0x04) { 0x0005FFFF, 0x02, GSI3, Zero }, Package (0x04) { 0x0005FFFF, 0x03, GSI0, Zero }, Package (0x04) { 0x0006FFFF, Zero, GSI2, Zero }, Package (0x04) { 0x0006FFFF, One, GSI3, Zero }, Package (0x04) { 0x0006FFFF, 0x02, GSI0, Zero }, Package (0x04) { 0x0006FFFF, 0x03, GSI1, Zero }, Package (0x04) { 0x0007FFFF, Zero, GSI3, Zero }, Package (0x04) { 0x0007FFFF, One, GSI0, Zero }, Package (0x04) { 0x0007FFFF, 0x02, GSI1, Zero }, Package (0x04) { 0x0007FFFF, 0x03, GSI2, Zero }, Package (0x04) { 0x0008FFFF, Zero, GSI0, Zero }, Package (0x04) { 0x0008FFFF, One, GSI1, Zero }, Package (0x04) { 0x0008FFFF, 0x02, GSI2, Zero }, Package (0x04) { 0x0008FFFF, 0x03, GSI3, Zero }, Package (0x04) { 0x0009FFFF, Zero, GSI1, Zero }, Package (0x04) { 0x0009FFFF, One, GSI2, Zero }, Package (0x04) { 0x0009FFFF, 0x02, GSI3, Zero }, Package (0x04) { 0x0009FFFF, 0x03, GSI0, Zero }, Package (0x04) { 0x000AFFFF, Zero, GSI2, Zero }, Package (0x04) { 0x000AFFFF, One, GSI3, Zero }, Package (0x04) { 0x000AFFFF, 0x02, GSI0, Zero }, Package (0x04) { 0x000AFFFF, 0x03, GSI1, Zero }, Package (0x04) { 0x000BFFFF, Zero, GSI3, Zero }, Package (0x04) { 0x000BFFFF, One, GSI0, Zero }, Package (0x04) { 0x000BFFFF, 0x02, GSI1, Zero }, Package (0x04) { 0x000BFFFF, 0x03, GSI2, Zero }, Package (0x04) { 0x000CFFFF, Zero, GSI0, Zero }, Package (0x04) { 0x000CFFFF, One, GSI1, Zero }, Package (0x04) { 0x000CFFFF, 0x02, GSI2, Zero }, Package (0x04) { 0x000CFFFF, 0x03, GSI3, Zero }, Package (0x04) { 0x000DFFFF, Zero, GSI1, Zero }, Package (0x04) { 0x000DFFFF, One, GSI2, Zero }, Package (0x04) { 0x000DFFFF, 0x02, GSI3, Zero }, Package (0x04) { 0x000DFFFF, 0x03, GSI0, Zero }, Package (0x04) { 0x000EFFFF, Zero, GSI2, Zero }, Package (0x04) { 0x000EFFFF, One, GSI3, Zero }, Package (0x04) { 0x000EFFFF, 0x02, GSI0, Zero }, Package (0x04) { 0x000EFFFF, 0x03, GSI1, Zero }, Package (0x04) { 0x000FFFFF, Zero, GSI3, Zero }, Package (0x04) { 0x000FFFFF, One, GSI0, Zero }, Package (0x04) { 0x000FFFFF, 0x02, GSI1, Zero }, Package (0x04) { 0x000FFFFF, 0x03, GSI2, Zero }, Package (0x04) { 0x0010FFFF, Zero, GSI0, Zero }, Package (0x04) { 0x0010FFFF, One, GSI1, Zero }, Package (0x04) { 0x0010FFFF, 0x02, GSI2, Zero }, Package (0x04) { 0x0010FFFF, 0x03, GSI3, Zero }, Package (0x04) { 0x0011FFFF, Zero, GSI1, Zero }, Package (0x04) { 0x0011FFFF, One, GSI2, Zero }, Package (0x04) { 0x0011FFFF, 0x02, GSI3, Zero }, Package (0x04) { 0x0011FFFF, 0x03, GSI0, Zero }, Package (0x04) { 0x0012FFFF, Zero, GSI2, Zero }, Package (0x04) { 0x0012FFFF, One, GSI3, Zero }, Package (0x04) { 0x0012FFFF, 0x02, GSI0, Zero }, Package (0x04) { 0x0012FFFF, 0x03, GSI1, Zero }, Package (0x04) { 0x0013FFFF, Zero, GSI3, Zero }, Package (0x04) { 0x0013FFFF, One, GSI0, Zero }, Package (0x04) { 0x0013FFFF, 0x02, GSI1, Zero }, Package (0x04) { 0x0013FFFF, 0x03, GSI2, Zero }, Package (0x04) { 0x0014FFFF, Zero, GSI0, Zero }, Package (0x04) { 0x0014FFFF, One, GSI1, Zero }, Package (0x04) { 0x0014FFFF, 0x02, GSI2, Zero }, Package (0x04) { 0x0014FFFF, 0x03, GSI3, Zero }, Package (0x04) { 0x0015FFFF, Zero, GSI1, Zero }, Package (0x04) { 0x0015FFFF, One, GSI2, Zero }, Package (0x04) { 0x0015FFFF, 0x02, GSI3, Zero }, Package (0x04) { 0x0015FFFF, 0x03, GSI0, Zero }, Package (0x04) { 0x0016FFFF, Zero, GSI2, Zero }, Package (0x04) { 0x0016FFFF, One, GSI3, Zero }, Package (0x04) { 0x0016FFFF, 0x02, GSI0, Zero }, Package (0x04) { 0x0016FFFF, 0x03, GSI1, Zero }, Package (0x04) { 0x0017FFFF, Zero, GSI3, Zero }, Package (0x04) { 0x0017FFFF, One, GSI0, Zero }, Package (0x04) { 0x0017FFFF, 0x02, GSI1, Zero }, Package (0x04) { 0x0017FFFF, 0x03, GSI2, Zero }, Package (0x04) { 0x0018FFFF, Zero, GSI0, Zero }, Package (0x04) { 0x0018FFFF, One, GSI1, Zero }, Package (0x04) { 0x0018FFFF, 0x02, GSI2, Zero }, Package (0x04) { 0x0018FFFF, 0x03, GSI3, Zero }, Package (0x04) { 0x0019FFFF, Zero, GSI1, Zero }, Package (0x04) { 0x0019FFFF, One, GSI2, Zero }, Package (0x04) { 0x0019FFFF, 0x02, GSI3, Zero }, Package (0x04) { 0x0019FFFF, 0x03, GSI0, Zero }, Package (0x04) { 0x001AFFFF, Zero, GSI2, Zero }, Package (0x04) { 0x001AFFFF, One, GSI3, Zero }, Package (0x04) { 0x001AFFFF, 0x02, GSI0, Zero }, Package (0x04) { 0x001AFFFF, 0x03, GSI1, Zero }, Package (0x04) { 0x001BFFFF, Zero, GSI3, Zero }, Package (0x04) { 0x001BFFFF, One, GSI0, Zero }, Package (0x04) { 0x001BFFFF, 0x02, GSI1, Zero }, Package (0x04) { 0x001BFFFF, 0x03, GSI2, Zero }, Package (0x04) { 0x001CFFFF, Zero, GSI0, Zero }, Package (0x04) { 0x001CFFFF, One, GSI1, Zero }, Package (0x04) { 0x001CFFFF, 0x02, GSI2, Zero }, Package (0x04) { 0x001CFFFF, 0x03, GSI3, Zero }, Package (0x04) { 0x001DFFFF, Zero, GSI1, Zero }, Package (0x04) { 0x001DFFFF, One, GSI2, Zero }, Package (0x04) { 0x001DFFFF, 0x02, GSI3, Zero }, Package (0x04) { 0x001DFFFF, 0x03, GSI0, Zero }, Package (0x04) { 0x001EFFFF, Zero, GSI2, Zero }, Package (0x04) { 0x001EFFFF, One, GSI3, Zero }, Package (0x04) { 0x001EFFFF, 0x02, GSI0, Zero }, Package (0x04) { 0x001EFFFF, 0x03, GSI1, Zero }, Package (0x04) { 0x001FFFFF, Zero, GSI3, Zero }, Package (0x04) { 0x001FFFFF, One, GSI0, Zero }, Package (0x04) { 0x001FFFFF, 0x02, GSI1, Zero }, Package (0x04) { 0x001FFFFF, 0x03, GSI2, Zero } }) Device (GSI0) { Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID Name (_UID, Zero) // _UID: Unique ID Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings { Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) { 0x00000023, } }) Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) { 0x00000023, } }) Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings { } } Device (GSI1) { Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID Name (_UID, One) // _UID: Unique ID Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings { Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) { 0x00000024, } }) Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) { 0x00000024, } }) Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings { } } Device (GSI2) { Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID Name (_UID, 0x02) // _UID: Unique ID Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings { Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) { 0x00000025, } }) Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) { 0x00000025, } }) Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings { } } Device (GSI3) { Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID Name (_UID, 0x03) // _UID: Unique ID Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings { Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) { 0x00000026, } }) Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) { 0x00000026, } }) Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings { } } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, // Granularity 0x60130000, // Range Minimum 0x6212FFFF, // Range Maximum 0x00000000, // Translation Offset 0x02000000, // Length ,, , AddressRangeMemory, TypeStatic) QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x0000000000000000, // Granularity 0x0000090000000000, // Range Minimum 0x00000900000FFFFF, // Range Maximum 0x0000000000000000, // Translation Offset 0x0000000000100000, // Length ,, , AddressRangeMemory, TypeStatic) WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, 0x0000, // Granularity 0x00C0, // Range Minimum 0x00FF, // Range Maximum 0x0000, // Translation Offset 0x0040, // Length ,, ) }) Device (RES0) { Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, 0x0000000000000000, // Granularity 0x00000000FC000000, // Range Minimum 0x00000000FFFFFFFF, // Range Maximum 0x0000000000000000, // Translation Offset 0x0000000004000000, // Length ,, , AddressRangeMemory, TypeStatic) }) Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } } Name (SUPP, Zero) Name (CTRL, Zero) Name (SUPC, Zero) Name (CTRC, Zero) Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities { CreateDWordField (Arg3, Zero, CDW1) If (((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */) || (Arg0 == ToUUID ("68f2d50b-c469-4d8a-bd3d-941a103fd3fc") /* Unknown UUID */))) { CreateDWordField (Arg3, 0x04, CDW2) CreateDWordField (Arg3, 0x08, CDW3) Local0 = CDW3 /* \_SB_.CXL0._OSC.CDW3 */ Local0 &= 0x1F If ((Arg1 != One)) { CDW1 |= 0x08 } If ((CDW3 != Local0)) { CDW1 |= 0x10 } SUPP = CDW2 /* \_SB_.CXL0._OSC.CDW2 */ CTRL = CDW3 /* \_SB_.CXL0._OSC.CDW3 */ CDW3 = Local0 If ((Arg0 == ToUUID ("68f2d50b-c469-4d8a-bd3d-941a103fd3fc") /* Unknown UUID */)) { CreateDWordField (Arg3, 0x0C, CDW4) CreateDWordField (Arg3, 0x10, CDW5) SUPC = CDW4 /* \_SB_.CXL0._OSC.CDW4 */ CTRC = CDW5 /* \_SB_.CXL0._OSC.CDW5 */ CDW5 |= One } Return (Arg3) } Else { CDW1 |= 0x04 Return (Arg3) } } } CEDT: [000h 0000 004h] Signature : "CEDT" [CXL Early Discovery Table] [004h 0004 004h] Table Length : 000000A8 [008h 0008 001h] Revision : 01 [009h 0009 001h] Checksum : 50 [00Ah 0010 006h] Oem ID : "LINARO" [010h 0016 008h] Oem Table ID : "SBSAQEMU" [018h 0024 004h] Oem Revision : 20240625 [01Ch 0028 004h] Asl Compiler ID : "LNRO" [020h 0032 004h] Asl Compiler Revision : 00000001 [024h 0036 001h] Subtable Type : 00 [CXL Host Bridge Structure] [025h 0037 001h] Reserved : 00 [026h 0038 002h] Length : 0020 [028h 0040 004h] Associated host bridge : 00000001 [02Ch 0044 004h] Specification version : 00000001 [030h 0048 004h] Reserved : 00000000 [034h 0052 008h] Register base : 0000000060120000 [03Ch 0060 008h] Register length : 0000000000010000 [044h 0068 001h] Subtable Type : 01 [CXL Fixed Memory Window Structure] [045h 0069 001h] Reserved : 00 [046h 0070 002h] Length : 0064 [048h 0072 004h] Reserved : 00000000 [04Ch 0076 008h] Window base address : 00000A0000000000 [054h 0084 008h] Window size : 0000010000000000 [05Ch 0092 001h] Interleave Members : 00 [05Dh 0093 001h] Interleave Arithmetic : 00 [05Eh 0094 002h] Reserved : 0000 [060h 0096 004h] Granularity : 00000000 [064h 0100 002h] Restrictions : 000F [066h 0102 002h] QtgId : 0001 [068h 0104 004h] First Target : 00000001 Link: [1]: https://lore.kernel.org/linux-cxl/20220616141950.23374-2-Jonathan.Cameron@h… [2]: https://edk2.groups.io/g/devel/topic/rfc_edk2_patch_v3_0_1/109403423# Yuquan Wang (1): SbsaQemu: Support basic CXL enablement Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 23 +- .../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 19 + Silicon/Qemu/SbsaQemu/AcpiTables/Cedt.aslc | 69 +++ Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 401 +++++++++++++++++- Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc | 2 +- Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 34 +- 6 files changed, 537 insertions(+), 11 deletions(-) create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Cedt.aslc -- 2.34.1

6 months, 1 week

1
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[RFC PATCH edk2-platforms v2 0/1] add basic support for CXL on sbsa-ref

by Yuquan Wang

v1 -> v2: - PCDs values about CXL exclusive MMIO32 & MMIO64 space - CXL Bus range: 0xc0 ~ 0xff - PCIE ecam space & Cxl ecam space - CEDT format RFC because - Many contents are ported from Jonathan' patch on qemu virt design - Bring plenty of PCDs values and modifying the original PCIE values - Less experience and not particularly confident in ACPI area This series leverages Jonathan's patches[1] to add acpi0016 & acpi0017 objects into the previous DSDT table of sbsa-ref. Since the acpi0016 implementation model on qemu side is the pxb-cxl, this cxl Bus would share ECAM sapce of PCIE Bus. Thus I divide some space from Pcie Ecam to support cxl-related values. To prevent breaking the original pcie mmio space, this adds exclusive mmio32 & mmio64 space for cxl host. This defines the pcie bus range of cxl host is 0xc0 ~ 0xff, since the pxb-cxl-host as well as cxl components on it would occupy the original pcie buses, the original pcie ecam space should divided some range for pxb-cxl-host. Based on the new CEDT definitions patch on edk2[2], this series adds a static Cedt.aslc to support the [SBSA_CXL_HOST] & [SBSA_CXL_FIXED_WINDOW] space on sbsa-ref. Link: [1]: https://lore.kernel.org/linux-cxl/20220616141950.23374-2-Jonathan.Cameron@h… [2]: https://edk2.groups.io/g/devel/topic/rfc_edk2_patch_v3_0_1/109403423# Yuquan Wang (1): SbsaQemu: Support basic CXL enablement Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 23 +- .../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 19 + Silicon/Qemu/SbsaQemu/AcpiTables/Cedt.aslc | 69 +++ Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 401 +++++++++++++++++- Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc | 2 +- Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 34 +- 6 files changed, 537 insertions(+), 11 deletions(-) create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Cedt.aslc -- 2.34.1

6 months, 1 week

1
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BSA/SBSA checklist page

by Marcin Juszkiewicz

During last days I worked on updating my BSA/SBSA checklist page: https://marcin.juszkiewicz.com.pl/download/tables/bsa-sbsa.html It now shows all tags used in either (S)BSA checklist or in (S)BSA ACS checklist. All in their expected sections. Also shows a column with state of SBSA Reference Platform in QEMU.

7 months, 3 weeks

1
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[RFC PATCH 0/2] Sbsa-ref CXL Enablement

by Yuquan Wang

RFC because - Many contents are ported from Jonathan' patch on qemu virt design - Bring plenty of PCDs values and modifying the original PCIE values - Less experience and not particularly confident in ACPI area so this might be stupidly broken in a way I've not considered. Currently the base CXL support for arm platforms is only on Jonathan's patches[1] which have not yet merged into upstream. SBSA-REF can be more like a real machine, thus the support of cxl could be meaningful. Regard to the burden of edk2 firmware, I try to build a static CEDT table and add acpi0016, acpi0017 objects on DSDT at the initial development phase[2][3]. Hence it doesn't need to communicate cxl contents via DT to edk2. This series leverages Jonathan's patches[1] to design [SBSA_CXL_HOST] and [SBSA_CXL_FIXED_WINDOW] spaces for sbsa-ref layout. For [SBSA_CXL_HOST], new memory layout places 1M space for 16 host bridge register regions in the sbsa-ref memmap. In addition, this only creates a default pxb-cxl (bus_nr=0xfe) bridge with one cxl-rp on sbsa-ref, so only one cxl device could be added by user on this cxl Bus. With the 'create_pxb_cxl', users don't need to input '-device pxb-cxl' and '-device cxl-rp' parameters. For [SBSA_CXL_FIXED_WINDOW], this extends 1TB space from the hole above RAM Memory [SBSA_MEM] for CXL Fixed Memory Window. 0xA0000000000 is chosen as the base address of this space because of 3 reasons: 1) It is more suitable to choose a static address instead of that implementation in virt, since a dynamic address space layout of sbsa-ref is not appropriate for its original purpose as a reference platform. 2) The Hotplug Memory address range should in the range of maximum addressable range of sbsa-ref platform(0x10000000000-0x80ffffffffff). It is satisfied the requirements of memory hotplug in linux kernel. 3) The start pfn of CFMW should exceed the reserved_pfn_range for onlined numa node. Based on 'cxl_fmws_link_targets', this adds a new function 'sbsa_cxl_fmws_link_targets' for binding cfmws.target with the default pxb-cxl-bus on sbsa-ref. In addition, this also adds 'create_cxl_fixed_window_region' which based on 'machine_set_cfmw' to support creating a static cfmw region on sbsa-ref, so users don't need to input '-M cxl-fmw' parameter. Thus, to run sbsa-ref with a cxl device could use: qemu-system-aarch64 \ -machine sbsa-ref \ -cpu cortex-a57 \ -smp 4 \ -m 4G \ -object memory-backend-ram,size=2G,id=mem0 \ -numa node,nodeid=0,cpus=0-1,memdev=mem0 \ -object memory-backend-ram,size=2G,id=mem1 \ -numa node,nodeid=1,cpus=2-3,memdev=mem1 \ -object memory-backend-file,id=mem2,mem-path=/tmp/mem2,size=256M,share=true \ -device cxl-type3,bus=cxl.0,volatile-memdev=mem2,id=cxl-mem1 \ -hda ubuntu.ext4 \ -pflash SBSA_FLASH0.fd \ -pflash SBSA_FLASH1.fd \ This series patches are here to hopefully some comments to guide me! Link: [1]: https://lore.kernel.org/linux-cxl/20220616141950.23374-1-Jonathan.Cameron@h… [2]: https://edk2.groups.io/g/devel/topic/rfc_patch_0_1/108173029 [3]: https://edk2.groups.io/g/devel/topic/rfc_patch_edk2_platforms/108173682 Yuquan Wang (2): hw/arm/sbsa-ref: Enable CXL Host Bridge by pxb-cxl hw/arm/sbsa-ref: Support CXL Fixed Memory Window hw/arm/sbsa-ref.c | 127 +++++++++++++++++++++++++++- hw/cxl/cxl-host-stubs.c | 1 + hw/cxl/cxl-host.c | 2 +- hw/pci-bridge/pci_expander_bridge.c | 1 - include/hw/cxl/cxl_host.h | 1 + include/hw/pci/pci_bridge.h | 1 + 6 files changed, 128 insertions(+), 5 deletions(-) -- 2.34.1 信息安全声明：本邮件包含信息归发件人所在组织所有,发件人所在组织对该邮件拥有所有权利。请接收者注意保密,未经发件人书面许可,不得向任何第三方组织和个人透露本邮件所含信息。 Information Security Notice: The information contained in this mail is solely property of the sender's organization.This mail communication is confidential.Recipients named above are obligated to maintain secrecy and are not permitted to disclose the contents of this communication to others.

8 months, 2 weeks

2
1
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[RFC PATCH 0/1] MdePkg/IndustryStandard: add definitions for ACPI 6.4 CEDT

by Yuquan Wang

RFC because - Less experience and not particularly confident in edk2 area so this might be stupidly broken in a way I've not considered. I am trying to support cxl on Qemu sbsa-ref platform, but it relies on CXL ACPI elements within compiled UEFI flash instead of virt/i386 using qemu-build-Acpi tables. Thus I create the header file CXLEarlyDiscoveryTable.h as the fundamental format for CEDT building in edk2-platforms. Yuquan Wang (1): MdePkg/IndustryStandard: add definitions for ACPI 6.4 CEDT MdePkg/Include/IndustryStandard/Acpi64.h | 5 ++ .../IndustryStandard/CXLEarlyDiscoveryTable.h | 69 +++++++++++++++++++ 2 files changed, 74 insertions(+) create mode 100644 MdePkg/Include/IndustryStandard/CXLEarlyDiscoveryTable.h -- 2.34.1 信息安全声明：本邮件包含信息归发件人所在组织所有,发件人所在组织对该邮件拥有所有权利。请接收者注意保密,未经发件人书面许可,不得向任何第三方组织和个人透露本邮件所含信息。 Information Security Notice: The information contained in this mail is solely property of the sender's organization.This mail communication is confidential.Recipients named above are obligated to maintain secrecy and are not permitted to disclose the contents of this communication to others.

8 months, 2 weeks

1
0
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[RFC PATCH 1/1] MdePkg/IndustryStandard: add definitions for ACPI 6.4 CEDT

by Yuquan Wang

This adds #defines and struct typedefs for the various structure types in the ACPI 6.4 CXL Early Discovery Table (CEDT). Signed-off-by: Yuquan Wang <wangyuquan1236(a)phytium.com.cn> --- MdePkg/Include/IndustryStandard/Acpi64.h | 5 ++ .../IndustryStandard/CXLEarlyDiscoveryTable.h | 69 +++++++++++++++++++ 2 files changed, 74 insertions(+) create mode 100644 MdePkg/Include/IndustryStandard/CXLEarlyDiscoveryTable.h diff --git a/MdePkg/Include/IndustryStandard/Acpi64.h b/MdePkg/Include/IndustryStandard/Acpi64.h index bbe6a3c9eb..c988de8ebf 100644 --- a/MdePkg/Include/IndustryStandard/Acpi64.h +++ b/MdePkg/Include/IndustryStandard/Acpi64.h @@ -3169,6 +3169,11 @@ typedef struct { /// #define EFI_ACPI_6_4_XEN_PROJECT_TABLE_SIGNATURE SIGNATURE_32('X', 'E', 'N', 'V') +/// +/// "CEDT" CXL Early Discovery Table +/// +#define EFI_ACPI_6_4_CXL_EARLY_DISCOVERY_TABLE_SIGNATURE SIGNATURE_32 ('C', 'E', 'D', 'T') + #pragma pack() #endif diff --git a/MdePkg/Include/IndustryStandard/CXLEarlyDiscoveryTable.h b/MdePkg/Include/IndustryStandard/CXLEarlyDiscoveryTable.h new file mode 100644 index 0000000000..84f88dc737 --- /dev/null +++ b/MdePkg/Include/IndustryStandard/CXLEarlyDiscoveryTable.h @@ -0,0 +1,69 @@ +/** @file + ACPI CXL Early Discovery Table (CEDT) definitions. + + Copyright (c) 2024, Phytium Technology Co Ltd. All rights reserved. + +**/ + +#ifndef __CXL_Early_Discovery_TABLE_H__ +#define __CXL_Early_Discovery_TABLE_H__ + +#include <IndustryStandard/Acpi.h> +#include <IndustryStandard/Acpi64.h> + +#define EFI_ACPI_CXL_Early_Discovery_TABLE_REVISION_01 0x1 //CXL2.0 +#define EFI_ACPI_CXL_Early_Discovery_TABLE_REVISION_02 0x2 //CXL3.1 + +#define EFI_ACPI_CEDT_TYPE_CHBS 0x0 +#define EFI_ACPI_CEDT_TYPE_CFMWS 0x1 + +#pragma pack(1) + +/// +/// Table header +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; +} EFI_ACPI_6_4_CXL_Early_Discovery_TABLE; + +/// +/// Node header definition shared by all structure types +/// +typedef struct { + UINT8 Type; + UINT8 Reserved; + UINT16 Length; +} EFI_ACPI_6_4_CEDT_Structure; + +/// +/// Definition for CXL Host Bridge Structure +/// +typedef struct { + EFI_ACPI_6_4_CEDT_Structure header; + UINT32 UID; + UINT32 CXLVersion; + UINT32 Reserved; + UINT64 Base; + UINT64 Length; +} EFI_ACPI_6_4_CXL_Host_Bridge_Structure; + +/// +/// Definition for CXL Fixed Memory Window Structure +/// +typedef struct { + EFI_ACPI_6_4_CEDT_Structure header; + UINT32 Reserved; + UINT64 BaseHPA; + UINT64 WindowSize; + UINT8 InterleaveMembers; + UINT8 InterleaveArithmetic; + UINT16 Reserved1; + UINT32 Granularity; + UINT16 Restrictions; + UINT16 QtgId; + UINT32 FirstTarget; +} EFI_ACPI_6_4_CXL_Fixed_Memory_Window_Structure; + +#pragma pack() + +#endif -- 2.34.1 信息安全声明：本邮件包含信息归发件人所在组织所有,发件人所在组织对该邮件拥有所有权利。请接收者注意保密,未经发件人书面许可,不得向任何第三方组织和个人透露本邮件所含信息。 Information Security Notice: The information contained in this mail is solely property of the sender's organization.This mail communication is confidential.Recipients named above are obligated to maintain secrecy and are not permitted to disclose the contents of this communication to others.

8 months, 2 weeks

1
0
0 0

[RFC PATCH 2/2] hw/arm/sbsa-ref: Support CXL Fixed Memory Window

by Yuquan Wang

In order to provide CFMWs on sbsa-ref, this extends 1TB space from the hole above RAM Memory [SBSA_MEM] for CXL Fixed Memory Window. 0xA0000000000 is chosen as the base address of this space because of 3 reasons: 1) It is more suitable to choose a static address instead of that implementation in virt, since a dynamic address space layout of sbsa-ref is not appropriate for its original purpose as a reference platform. 2) The Hotplug Memory address range should in the range of maximum addressable range of sbsa-ref platform(0x10000000000-0x80ffffffffff). It is satisfied the requirements of memory hotplug in linux kernel. 3) The start pfn of CFMW should exceed the reserved_pfn_range for onlined numa node. Based on 'cxl_fmws_link_targets', this adds a new function 'sbsa_cxl_fmws_link_targets' for binding cfmws.target with the default pxb-cxl-bus on sbsa-ref. In addition, this also adds 'create_cxl_fixed_window_region' which based on 'machine_set_cfmw' to support creating a static cfmw region on sbsa-ref. Thus, to run sbsa-ref with a cxl device could use: qemu-system-aarch64 \ -machine sbsa-ref \ -cpu cortex-a57 \ -smp 4 \ -m 4G \ -object memory-backend-ram,size=2G,id=mem0 \ -numa node,nodeid=0,cpus=0-1,memdev=mem0 \ -object memory-backend-ram,size=2G,id=mem1 \ -numa node,nodeid=1,cpus=2-3,memdev=mem1 \ -object memory-backend-file,id=mem2,mem-path=/tmp/mem2,size=256M,share=true \ -device cxl-type3,bus=cxl.0,volatile-memdev=mem2,id=cxl-mem1 \ -hda ubuntu.ext4 \ -pflash SBSA_FLASH0.fd \ -pflash SBSA_FLASH1.fd \ I'm not sure if the new space layout would bring a series of bad influence, this patch is here to hopefully some comments to guide me! Signed-off-by: Yuquan Wang <wangyuquan1236(a)phytium.com.cn> --- hw/arm/sbsa-ref.c | 73 +++++++++++++++++++++++++++++ hw/cxl/cxl-host-stubs.c | 1 + hw/cxl/cxl-host.c | 2 +- hw/pci-bridge/pci_expander_bridge.c | 1 - include/hw/cxl/cxl_host.h | 1 + include/hw/pci/pci_bridge.h | 1 + 6 files changed, 77 insertions(+), 2 deletions(-) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index dc924d181e..b10865920e 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -100,6 +100,7 @@ enum { SBSA_AHCI, SBSA_XHCI, SBSA_CXL_HOST, + SBSA_CXL_FIXED_WINDOW, }; struct SBSAMachineState { @@ -152,6 +153,8 @@ static const MemMapEntry sbsa_ref_memmap[] = { /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */ [SBSA_PCIE_MMIO_HIGH] = { 0x100000000ULL, 0xFF00000000ULL }, [SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES }, + /* 1TB CXL FIXED WINDOW space */ + [SBSA_CXL_FIXED_WINDOW] = { 0xA0000000000ULL, 0x10000000000ULL }, }; static const int sbsa_ref_irqmap[] = { @@ -734,6 +737,72 @@ static void create_cxl_host_reg_region(SBSAMachineState *sms) memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_CXL_HOST].base, mr); } +static void create_cxl_fixed_window_region(SBSAMachineState *sms, MemoryRegion *mem) +{ + char cxl_host[] = "pxb-cxl-bus.0"; + CXLFixedMemoryWindowOptionsList *list; + hwaddr base, end; + GList *it; + strList host_target = { NULL, cxl_host }; + CXLFixedMemoryWindowOptions sbsa_ref_cfmwoptions = { + .size = 1 * TiB, + .has_interleave_granularity = false, + .targets = &host_target, + }; + CXLFixedMemoryWindowOptionsList sbsa_ref_cfmwlist = { NULL, &sbsa_ref_cfmwoptions }; + + for (list = &sbsa_ref_cfmwlist; list; list = list->next) { + cxl_fixed_memory_window_config(&sms->cxl_devices_state, list->value, &error_fatal); + } + + base = sbsa_ref_memmap[SBSA_CXL_FIXED_WINDOW].base; + end = base + sbsa_ref_memmap[SBSA_CXL_FIXED_WINDOW].size; + + for (it = sms->cxl_devices_state.fixed_windows; it; it = it->next) { + CXLFixedWindow *fw = it->data; + if (base + fw->size > end) { + error_report("CFMWS does not fit under PA limit"); + exit(EXIT_FAILURE); + } + + fw->base = base; + memory_region_init_io(&fw->mr, OBJECT(sms), &cfmws_ops, fw, + "cxl-fixed-memory-region", fw->size); + + memory_region_add_subregion(mem, fw->base, &fw->mr); + base += fw->size; + } +} + +static void sbsa_cxl_fmws_link_targets(SBSAMachineState *sms, + CXLState *cxl_state, Error **errp) +{ + PXBCXLDev *pxb = PXB_CXL_DEV(pci_bridge_get_device(sms->cxlbus)); + if (cxl_state && cxl_state->fixed_windows) { + GList *it; + + for (it = cxl_state->fixed_windows; it; it = it->next) { + CXLFixedWindow *fw = it->data; + int i; + + for (i = 0; i < fw->num_targets; i++) { + Object *o; + bool ambig; + + o = object_resolve_path_type(fw->targets[i], + TYPE_PXB_CXL_BUS, + &ambig); + if (!o) { + error_setg(errp, "Could not resolve CXLFM target %s", + fw->targets[i]); + return; + } + fw->target_hbs[i] = pxb; + } + } + } +} + static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size) { const SBSAMachineState *board = container_of(binfo, SBSAMachineState, @@ -869,8 +938,12 @@ static void sbsa_ref_init(MachineState *machine) create_cxl_host_reg_region(sms); + create_cxl_fixed_window_region(sms, sysmem); + cxl_hook_up_pxb_registers(sms->bus, &sms->cxl_devices_state, &error_fatal); + sbsa_cxl_fmws_link_targets(sms, &sms->cxl_devices_state, &error_fatal); + create_secure_ec(secure_sysmem); sms->bootinfo.ram_size = machine->ram_size; diff --git a/hw/cxl/cxl-host-stubs.c b/hw/cxl/cxl-host-stubs.c index cae4afcdde..d523be24a2 100644 --- a/hw/cxl/cxl-host-stubs.c +++ b/hw/cxl/cxl-host-stubs.c @@ -11,5 +11,6 @@ void cxl_fmws_link_targets(CXLState *stat, Error **errp) {}; void cxl_machine_init(Object *obj, CXLState *state) {}; void cxl_hook_up_pxb_registers(PCIBus *bus, CXLState *state, Error **errp) {}; +void cxl_fixed_memory_window_config(CXLState *cxl_state, CXLFixedMemoryWindowOptions *object, Error **errp) {}; const MemoryRegionOps cfmws_ops; diff --git a/hw/cxl/cxl-host.c b/hw/cxl/cxl-host.c index e9f2543c43..d408c7db15 100644 --- a/hw/cxl/cxl-host.c +++ b/hw/cxl/cxl-host.c @@ -22,7 +22,7 @@ #include "hw/pci/pcie_port.h" #include "hw/pci-bridge/pci_expander_bridge.h" -static void cxl_fixed_memory_window_config(CXLState *cxl_state, +void cxl_fixed_memory_window_config(CXLState *cxl_state, CXLFixedMemoryWindowOptions *object, Error **errp) { diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expander_bridge.c index 0411ad31ea..f5431443b9 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -38,7 +38,6 @@ DECLARE_INSTANCE_CHECKER(PXBBus, PXB_BUS, DECLARE_INSTANCE_CHECKER(PXBBus, PXB_PCIE_BUS, TYPE_PXB_PCIE_BUS) -#define TYPE_PXB_CXL_BUS "pxb-cxl-bus" DECLARE_INSTANCE_CHECKER(PXBBus, PXB_CXL_BUS, TYPE_PXB_CXL_BUS) diff --git a/include/hw/cxl/cxl_host.h b/include/hw/cxl/cxl_host.h index c9bc9c7c50..5fbf5a9347 100644 --- a/include/hw/cxl/cxl_host.h +++ b/include/hw/cxl/cxl_host.h @@ -16,6 +16,7 @@ void cxl_machine_init(Object *obj, CXLState *state); void cxl_fmws_link_targets(CXLState *stat, Error **errp); void cxl_hook_up_pxb_registers(PCIBus *bus, CXLState *state, Error **errp); +void cxl_fixed_memory_window_config(CXLState *cxl_state, CXLFixedMemoryWindowOptions *object, Error **errp); extern const MemoryRegionOps cfmws_ops; diff --git a/include/hw/pci/pci_bridge.h b/include/hw/pci/pci_bridge.h index 5cd452115a..5456e24883 100644 --- a/include/hw/pci/pci_bridge.h +++ b/include/hw/pci/pci_bridge.h @@ -102,6 +102,7 @@ typedef struct PXBPCIEDev { PXBDev parent_obj; } PXBPCIEDev; +#define TYPE_PXB_CXL_BUS "pxb-cxl-bus" #define TYPE_PXB_DEV "pxb" OBJECT_DECLARE_SIMPLE_TYPE(PXBDev, PXB_DEV) -- 2.34.1 信息安全声明：本邮件包含信息归发件人所在组织所有,发件人所在组织对该邮件拥有所有权利。请接收者注意保密,未经发件人书面许可,不得向任何第三方组织和个人透露本邮件所含信息。 Information Security Notice: The information contained in this mail is solely property of the sender's organization.This mail communication is confidential.Recipients named above are obligated to maintain secrecy and are not permitted to disclose the contents of this communication to others.

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