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Re: [Asa-dev] StanadloneMM shared memory location

by Graeme Gregory

On Fri, 21 Aug 2020, at 11:34 AM, Masahisa Kojima via Asa-dev wrote: > Hi all, > > I make StandaloneMM with secure varstore work on SBSA-QEMU. > > One item I would like to discuss is the location of non-secure shared memory > between UEFI and Secure-EL0(StandaloneMM). > > For StandaloneMM, non-secure shared memory must be defined > in compile time, because there is no method to know the > shared memory address between uefi and tf-a in runtime. > I maybe missing something here, but ARM-TF can and does pass on a DT to edk2, can this not be defined there? Graeme > I allocated this non-secure shared memory at the bottom of the DRAM, > because DRAM size varies depending on the QEMU parameter. > > DRAM layout is as follows(when the DRAM size is 1GB) > 0x10000000000 - 0x10000FFFFFF(16MB) non-secure shared memory for StandaloneMM > 0x10001000000 - 0x1003FFFFFFF(1GB - 16MB) > > Does anyone have comments on this? > My concern is allocating something at the bottom of the DRAM is not > the usual implementation? > # Other packages like SGI allocate it at the top of DRAM. > > https://github.com/tianocore/edk2-platforms/blob/master/Platform/ARM/SgiPkg… > > --- patch --- > diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc > b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc > index 7d9a9cc50bf3..7ec5669615f0 100644 > --- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc > +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc > @@ -387,7 +387,8 @@ [PcdsFixedAtBuild.common] > gArmTokenSpaceGuid.PcdVFPEnabled|1 > > # System Memory Base -- fixed > - gArmTokenSpaceGuid.PcdSystemMemoryBase|0x10000000000 > + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x10001000000 > > diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuMem.c > b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuMem.c > index 8c2eb0b6a028..7af9f5a4a1dc 100644 > --- a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuMem.c > +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuMem.c > @@ -73,8 +73,13 @@ SbsaQemuLibConstructor ( > } > } > > + // For StandaloneMM Non-Secure Shared buffer, reserve 16MB > + // at the bottom of DRAM. > + NewSize -= 0x1000000; > + > // Make sure the start of DRAM matches our expectation > - ASSERT (FixedPcdGet64 (PcdSystemMemoryBase) == NewBase); > + // remove base address check > +// ASSERT (FixedPcdGet64 (PcdSystemMemoryBase) == NewBase); > PcdStatus = PcdSet64S (PcdSystemMemorySize, NewSize); > ------ > > Regards, > Masahisa > -- > Asa-dev mailing list > Asa-dev(a)op-lists.linaro.org > https://op-lists.linaro.org/mailman/listinfo/asa-dev >

3 years, 9 months

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StanadloneMM shared memory location

by Masahisa Kojima

Hi all, I make StandaloneMM with secure varstore work on SBSA-QEMU. One item I would like to discuss is the location of non-secure shared memory between UEFI and Secure-EL0(StandaloneMM). For StandaloneMM, non-secure shared memory must be defined in compile time, because there is no method to know the shared memory address between uefi and tf-a in runtime. I allocated this non-secure shared memory at the bottom of the DRAM, because DRAM size varies depending on the QEMU parameter. DRAM layout is as follows(when the DRAM size is 1GB) 0x10000000000 - 0x10000FFFFFF(16MB) non-secure shared memory for StandaloneMM 0x10001000000 - 0x1003FFFFFFF(1GB - 16MB) Does anyone have comments on this? My concern is allocating something at the bottom of the DRAM is not the usual implementation? # Other packages like SGI allocate it at the top of DRAM. https://github.com/tianocore/edk2-platforms/blob/master/Platform/ARM/SgiPkg… --- patch --- diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc index 7d9a9cc50bf3..7ec5669615f0 100644 --- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc @@ -387,7 +387,8 @@ [PcdsFixedAtBuild.common] gArmTokenSpaceGuid.PcdVFPEnabled|1 # System Memory Base -- fixed - gArmTokenSpaceGuid.PcdSystemMemoryBase|0x10000000000 + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x10001000000 diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuMem.c b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuMem.c index 8c2eb0b6a028..7af9f5a4a1dc 100644 --- a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuMem.c +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuMem.c @@ -73,8 +73,13 @@ SbsaQemuLibConstructor ( } } + // For StandaloneMM Non-Secure Shared buffer, reserve 16MB + // at the bottom of DRAM. + NewSize -= 0x1000000; + // Make sure the start of DRAM matches our expectation - ASSERT (FixedPcdGet64 (PcdSystemMemoryBase) == NewBase); + // remove base address check +// ASSERT (FixedPcdGet64 (PcdSystemMemoryBase) == NewBase); PcdStatus = PcdSet64S (PcdSystemMemorySize, NewSize); ------ Regards, Masahisa

3 years, 9 months

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[PATCH v2 0/5] Add ACPI tables support for SbsaQemu

by Tanmay Jagdale

This patch series adds support for ACPI tables on the SBSA Qemu platform. We are using a pseudo static approach to create the ACPI tables. Some of the tables such as DSDT, MCFG, SPCR, GTDT are created in a static way at compile time because they hold a fixed configuration and there are no changes at runtime. The MADT and SSDT are dependant on the number of CPUs and hence they are created at runtime based on the number of CPUs the user has requested. Changes in V2: - Add support for SSDT table creation - Addressed the comments of V1 patch o Moved PCI changes to a separate patch o Used Pcd to create common ACPI fields such as OEMID, OEM revision etc. o Created an Include directory to hold the common header files for ACPI Tanmay Jagdale (5): SbsaQemu: Initial support for static ACPI tables SbsaQemu: AcpiTables: Add PCI support and MCFG Table SbsaQemu: Add new ACPI driver and FDT parser to count CPU SbsaQemu: AcpiDxe: Create MADT table at runtime SbsaQemu: AcpiDxe: Add support to SSDT Table Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 12 +- Platform/Qemu/SbsaQemu/SbsaQemu.fdf | 9 + Silicon/Qemu/SbsaQemu/Acpi.dsc.inc | 36 ++ .../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 46 ++ Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 449 ++++++++++++++++++ Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc | 80 ++++ Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc | 67 +++ Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc | 43 ++ Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc | 53 +++ .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 379 +++++++++++++++ .../SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 67 +++ .../SbsaQemuPlatformDxe.inf | 1 - .../Include/IndustryStandard/SbsaQemuAcpi.h | 81 ++++ Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 8 +- 14 files changed, 1326 insertions(+), 5 deletions(-) create mode 100644 Silicon/Qemu/SbsaQemu/Acpi.dsc.inc create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc create mode 100644 Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c create mode 100644 Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf create mode 100644 Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h -- 2.28.0

3 years, 9 months

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redundant code in tf-a qemu_sbsa port

by Leif Lindholm

Hi all, We've started looking at the TF-A qemu_sbsa port a bit, and found some things that were carried over from the mach-virt port for no good reason: Looking at plat/qemu/qemu_sbsa/platform.mk: - lib/cpus/aarch64/aem_generic.S is for fast models/foundation model. - although we may want to add a "generic armv8 cpu" to TF-A at some point, to reduce synchronization needs when bumping the cpu used by sbsa-ref in upstream QEMU. - lib/cpus/aarch64/cortex_a53.S is not supported by sbsa-ref, nor does the A53 support enough physical address bits to be able to control this platform. - drivers/io/io_semihosting.c, lib/semihosting/semihosting.c, and lib/semihosting/${ARCH}/semihosting_call.S are not actually used. But there *are* some other bits of qemu/common code which needs to be cinditionalized-out if these files aren't included. - plat/common/plat_psci_common.c - all of the ${ARCH} stanzas should just be 'aarch64', this platform cannot be booted in aarch32. - plat/common/plat_psci_common.c isn't usefully hooked up to anything at the moment, but we can fix that when we get to actually implementing useful PSCI. That file may simply not belong in 'common'. / Leif

3 years, 9 months

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Luv test run results

by Marcin Juszkiewicz

I have played with ARM Enterprise ACS test suite yesterday locally. It can not be added to CI yet as it requires working watchdog and reset needs to function too (ASA-54). Part of it was run of Luv. I put results online as someone may find it interesting and useful: https://people.linaro.org/~marcin.juszkiewicz/sbsa/luv-results-2020-08-06--… I can add them to CI if this would be useful.

3 years, 9 months

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[PATCH 1/4] SbsaQemu: Initial support for static ACPI tables

by Tanmay Jagdale

Add the following static ACPI tables for the SBSA Qemu platform - DSDT - FADT - GTDT - MADT - MCFG - SPCR Currently we support 4 CPUs. Co-authored-by: Graeme Gregory <graeme.gregory(a)linaro.org> Co-authored-by: Jonathan Cameron <jonathan.cameron(a)huawei.com> Co-authored-by: Tanmay Jagdale <tanmay.jagdale(a)linaro.org> Signed-off-by: Tanmay Jagdale <tanmay.jagdale(a)linaro.org> --- Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 11 +- Platform/Qemu/SbsaQemu/SbsaQemu.fdf | 14 + Silicon/Qemu/SbsaQemu/Acpi.dsc.inc | 42 + Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.h | 61 + .../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 47 + Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 1400 +++++++++++++++++ Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc | 85 + Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc | 71 + Silicon/Qemu/SbsaQemu/AcpiTables/Madt.aslc | 85 + Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc | 50 + Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc | 122 ++ .../SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c | 6 + .../SbsaQemuPlatformDxe.inf | 10 + 13 files changed, 2003 insertions(+), 1 deletion(-) create mode 100644 Silicon/Qemu/SbsaQemu/Acpi.dsc.inc create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.h create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Madt.aslc create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc index 4db3ab4651..ac1398af8f 100644 --- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc @@ -300,6 +300,10 @@ DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0 gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320 + # Core and Cluster Count + gArmPlatformTokenSpaceGuid.PcdCoreCount|4 + gArmPlatformTokenSpaceGuid.PcdClusterCount|1 + # DEBUG_ASSERT_ENABLED 0x01 # DEBUG_PRINT_ENABLED 0x02 # DEBUG_CODE_ENABLED 0x04 @@ -376,7 +380,6 @@ DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE # gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack|TRUE - gArmPlatformTokenSpaceGuid.PcdCoreCount|1 gArmTokenSpaceGuid.PcdVFPEnabled|1 # System Memory Base -- fixed @@ -516,6 +519,7 @@ DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE ShellPkg/Application/Shell/Shell.inf { <LibraryClasses> ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf + NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewCommandLib.inf NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf @@ -675,3 +679,8 @@ DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + # + # ACPI Support +!include Silicon/Qemu/SbsaQemu/Acpi.dsc.inc + MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf b/Platform/Qemu/SbsaQemu/SbsaQemu.fdf index be7c78aceb..7f1a60e3ee 100644 --- a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.fdf @@ -227,6 +227,14 @@ READ_LOCK_STATUS = TRUE INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf + # + # ACPI support + # + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf + INF RuleOverride = ACPITABLE Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf + INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf + # # PCI support # @@ -301,3 +309,9 @@ READ_LOCK_STATUS = TRUE } !include ArmVirtPkg/ArmVirtRules.fdf.inc + +[Rule.Common.USER_DEFINED.ACPITABLE] + FILE FREEFORM = $(NAMED_GUID) { + RAW ACPI |.acpi + RAW ASL |.aml + } diff --git a/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc b/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc new file mode 100644 index 0000000000..76d0fac079 --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc @@ -0,0 +1,42 @@ +# +# Copyright (c) 2018, Linaro Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ + +[PcdsFeatureFlag] + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE + +[PcdsFixedAtBuild.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|"LNRO " + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x4153425341534253 # SBSA + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x20190910 + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x4f524e4c # LNRO + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|1 + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform +# +################################################################################ + +[Components.common] + # + # ACPI support + # + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf { + <LibraryClasses> + NULL|EmbeddedPkg/Library/PlatformHasAcpiLib/PlatformHasAcpiLib.inf + + <PcdsFixedAtBuild> + # support ACPI v5.0 or later + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20 + } + MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf + Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.h b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.h new file mode 100644 index 0000000000..a30ade5a92 --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.h @@ -0,0 +1,61 @@ +/** @file +* +* Copyright (c) 2013-2014, ARM Limited. All rights reserved. +* Copyright (c) 2018, Linaro Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#ifndef __ACPITABLES_H__ +#define __ACPITABLES_H__ + +// +// ACPI table information used to initialize tables. +// +#define EFI_ACPI_OEM_ID 'L','N','R','O',' ',' ' +#define EFI_ACPI_OEM_TABLE_ID SIGNATURE_64('S','B','S','A','S','B','S','A') +#define EFI_ACPI_OEM_REVISION FixedPcdGet32 (PcdAcpiDefaultOemRevision) +#define EFI_ACPI_CREATOR_ID SIGNATURE_32('L','N','R','O') +#define EFI_ACPI_CREATOR_REVISION FixedPcdGet32 (PcdAcpiDefaultCreatorRevision) + +// A macro to initialise the common header part of EFI ACPI tables as defined by +// EFI_ACPI_DESCRIPTION_HEADER structure. +#define __ACPI_HEADER(Signature, Type, Revision) { \ + Signature, /* UINT32 Signature */ \ + sizeof (Type), /* UINT32 Length */ \ + Revision, /* UINT8 Revision */ \ + 0, /* UINT8 Checksum */ \ + { EFI_ACPI_OEM_ID }, /* UINT8 OemId[6] */ \ + EFI_ACPI_OEM_TABLE_ID, /* UINT64 OemTableId */ \ + EFI_ACPI_OEM_REVISION, /* UINT32 OemRevision */ \ + EFI_ACPI_CREATOR_ID, /* UINT32 CreatorId */ \ + EFI_ACPI_CREATOR_REVISION /* UINT32 CreatorRevision */ \ + } + +#define EFI_ACPI_6_0_GIC_REDISTRIBUTOR_INIT(RedisRegionAddr, RedisDiscLength) \ + { \ + EFI_ACPI_6_0_GICR, \ + sizeof (EFI_ACPI_6_0_GICR_STRUCTURE), \ + 0, \ + RedisRegionAddr, \ + RedisDiscLength \ + } + +#define EFI_ACPI_6_0_GIC_ITS_FRAME_INIT(Id, PhysAddress) \ + { \ + EFI_ACPI_6_0_GIC_ITS, \ + sizeof (EFI_ACPI_6_0_GIC_ITS_STRUCTURE), \ + 0, \ + Id, \ + PhysAddress, \ + 0 \ + } + +#define SBSAQEMU_UART0_BASE 0x60000000 + +#define SBSAQEMU_PCI_SEG0_CONFIG_BASE 0xf0000000 +#define SBSAQEMU_PCI_SEG0_BUSNUM_MIN 0x00 +#define SBSAQEMU_PCI_SEG0_BUSNUM_MAX 0xFF + +#endif diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf new file mode 100644 index 0000000000..63d5754e16 --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf @@ -0,0 +1,47 @@ +## @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2014-2016, ARM Ltd. All rights reserved. +# Copyright (c) 2018, Linaro Ltd. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = SbsaAcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + +[Sources] + AcpiTables.h + Dsdt.asl + Fadt.aslc + Madt.aslc + Gtdt.aslc + Spcr.aslc + Mcfg.aslc + +[Packages] + ArmPlatformPkg/ArmPlatformPkg.dec + ArmPkg/ArmPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[FixedPcd] + gArmPlatformTokenSpaceGuid.PcdClusterCount + gArmPlatformTokenSpaceGuid.PcdCoreCount + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl new file mode 100644 index 0000000000..d63e22dd6b --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl @@ -0,0 +1,1400 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2014-2016, ARM Ltd. All rights reserved.<BR> + Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "AcpiTables.h" + +DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LNRO", "SBSA", + EFI_ACPI_OEM_REVISION) { + Scope (_SB) { + // + // A53x4 Processor declaration + // + Device (CP00) { // A53-0: Cluster 0, Cpu 0 + Name (_HID, "ACPI0007") + Name (_UID, 0) + } + + // UART PL011 + Device (COM0) { + Name (_HID, "ARMH0011") + Name (_UID, Zero) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0x60000000, 0x00001000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 33 } + }) + } + + Device(AHC0) { + Name(_HID, "LNRO001E") + Name(_CLS, Package (3) { + 0x01, + 0x06, + 0x01, + }) + Name(_CCA, 1) + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x60100000, 0x1000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 42 } + }) + } + + // + // USB EHCI Host Controller + // + Device(USB0){ + Name(_HID, "LNRO0D20") + Name(_CID, "PNP0D20") + + Method(_CRS, 0x0, Serialized){ + Name(RBUF, ResourceTemplate(){ + Memory32Fixed(ReadWrite, 0x60110000, 0x00010000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 43 } + }) + Return(RBUF) + } + + // + // Root Hub + // + Device(RHUB){ + Name(_ADR, 0x00000000) // Address of Root Hub should be 0 as per ACPI 5.0 spec + + // + // Ports connected to Root Hub + // + Device(HUB1){ + Name(_ADR, 0x00000001) + Name(_UPC, Package(){ + 0x00, // Port is NOT connectable + 0xFF, // Don't care + 0x00000000, // Reserved 0 must be zero + 0x00000000 // Reserved 1 must be zero + }) + + Device(PRT1){ + Name(_ADR, 0x00000001) + Name(_UPC, Package(){ + 0xFF, // Port is connectable + 0x00, // Port connector is A + 0x00000000, + 0x00000000 + }) + Name(_PLD, Package(){ + Buffer(0x10){ + 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + } + }) + } // USB0_RHUB_HUB1_PRT1 + Device(PRT2){ + Name(_ADR, 0x00000002) + Name(_UPC, Package(){ + 0xFF, // Port is connectable + 0x00, // Port connector is A + 0x00000000, + 0x00000000 + }) + Name(_PLD, Package(){ + Buffer(0x10){ + 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + } + }) + } // USB0_RHUB_HUB1_PRT2 + + Device(PRT3){ + Name(_ADR, 0x00000003) + Name(_UPC, Package(){ + 0xFF, // Port is connectable + 0x00, // Port connector is A + 0x00000000, + 0x00000000 + }) + Name(_PLD, Package(){ + Buffer(0x10){ + 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + } + }) + } // USB0_RHUB_HUB1_PRT3 + + Device(PRT4){ + Name(_ADR, 0x00000004) + Name(_UPC, Package(){ + 0xFF, // Port is connectable + 0x00, // Port connector is A + 0x00000000, + 0x00000000 + }) + Name(_PLD, Package(){ + Buffer(0x10){ + 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + } + }) + } // USB0_RHUB_HUB1_PRT4 + } // USB0_RHUB_HUB1 + } // USB0_RHUB + } // USB0 + + Device(PCI0) + { + Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge + Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge + Name(_SEG, Zero) // PCI Segment Group number + Name(_BBN, Zero) // PCI Base Bus Number + Name(_ADR, Zero) + Name(_UID, "PCI0") + Name(_CCA, One) // Initially mark the PCI coherent (for JunoR1) + + Method(_CBA, 0, NotSerialized) { + return (0xf0000000) + } + + Device (GSI0) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000023, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000023, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSI1) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000024, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000024, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSI2) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000025, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000025, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSI3) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000026, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000026, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Name (_PRT, Package () // _PRT: PCI Routing Table + { + Package () + { + 0x0000FFFF, + Zero, + GSI0, + Zero + }, + + Package () + { + 0x0000FFFF, + Zero, + GSI1, + Zero + }, + + Package () + { + 0x0000FFFF, + Zero, + GSI2, + Zero + }, + + Package () + { + 0x0000FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + GSI2, + Zero + }, + }) + + // Root complex resources + Method (_CRS, 0, Serialized) { + Name (RBUF, ResourceTemplate () { + WordBusNumber ( // Bus numbers assigned to this root + ResourceProducer, + MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + 0, // AddressMinimum - Minimum Bus Number + 255, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 256 // RangeLength - Number of Busses + ) + + DWordMemory ( // 32-bit BAR Windows + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x80000000, // Min Base Address + 0xEFFFFFFF, // Max Base Address + 0x00000000, // Translate + 0x70000000 // Length + ) + + QWordMemory ( // 64-bit BAR Windows + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x100000000, // Min Base Address + 0xFFFFFFFFFF, // Max Base Address + 0x00000000, // Translate + 0xFF00000000 // Length + ) + + DWordIo ( // IO window + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x00000000, // Granularity + 0x00000000, // Min Base Address + 0x0000ffff, // Max Base Address + 0x7fff0000, // Translate + 0x00010000, // Length + ,,,TypeTranslation + ) + }) // Name(RBUF) + + Return (RBUF) + } // Method(_CRS) + + Device (RES0) + { + Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x00000000F0000000, // Range Minimum + 0x00000000FFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000010000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + } + + // + // OS Control Handoff + // + Name(SUPP, Zero) // PCI _OSC Support Field value + Name(CTRL, Zero) // PCI _OSC Control Field value + + /* + See [1] 6.2.10, [2] 4.5 + */ + Method(_OSC,4) { + // Check for proper UUID + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + // Create DWord-adressable fields from the Capabilities Buffer + CreateDWordField(Arg3,0,CDW1) + CreateDWordField(Arg3,4,CDW2) + CreateDWordField(Arg3,8,CDW3) + + // Save Capabilities DWord2 & 3 + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // Only allow native hot plug control if OS supports: + // * ASPM + // * Clock PM + // * MSI/MSI-X + If(LNotEqual(And(SUPP, 0x16), 0x16)) { + And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits) + } + + // Always allow native PME, AER (no dependencies) + + // Never allow SHPC (no SHPC controller in this system) + And(CTRL,0x1D,CTRL) + + If(LNotEqual(Arg1,One)) { // Unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + + // Update DWORD3 in the buffer + Store(CTRL,CDW3) + Return(Arg3) + } Else { + Or(CDW1,4,CDW1) // Unrecognized UUID + Return(Arg3) + } + } // End _OSC + } + } // Scope (_SB) +} diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc new file mode 100644 index 0000000000..a0ec22abce --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc @@ -0,0 +1,85 @@ +/** @file +* Fixed ACPI Description Table (FADT) +* +* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved. +* Copyright (c) 2018, Linaro Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include <Library/AcpiLib.h> +#include <IndustryStandard/Acpi.h> + +#include "AcpiTables.h" + +EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { + __ACPI_HEADER ( + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE, + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION + ), + 0, // UINT32 FirmwareCtrl + 0, // UINT32 Dsdt + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0 + EFI_ACPI_6_0_PM_PROFILE_ENTERPRISE_SERVER, // UINT8 PreferredPmProfile + 0, // UINT16 SciInt + 0, // UINT32 SmiCmd + 0, // UINT8 AcpiEnable + 0, // UINT8 AcpiDisable + 0, // UINT8 S4BiosReq + 0, // UINT8 PstateCnt + 0, // UINT32 Pm1aEvtBlk + 0, // UINT32 Pm1bEvtBlk + 0, // UINT32 Pm1aCntBlk + 0, // UINT32 Pm1bCntBlk + 0, // UINT32 Pm2CntBlk + 0, // UINT32 PmTmrBlk + 0, // UINT32 Gpe0Blk + 0, // UINT32 Gpe1Blk + 0, // UINT8 Pm1EvtLen + 0, // UINT8 Pm1CntLen + 0, // UINT8 Pm2CntLen + 0, // UINT8 PmTmrLen + 0, // UINT8 Gpe0BlkLen + 0, // UINT8 Gpe1BlkLen + 0, // UINT8 Gpe1Base + 0, // UINT8 CstCnt + 0, // UINT16 PLvl2Lat + 0, // UINT16 PLvl3Lat + 0, // UINT16 FlushSize + 0, // UINT16 FlushStride + 0, // UINT8 DutyOffset + 0, // UINT8 DutyWidth + 0, // UINT8 DayAlrm + 0, // UINT8 MonAlrm + 0, // UINT8 Century + 0, // UINT16 IaPcBootArch + 0, // UINT8 Reserved1 + EFI_ACPI_6_0_HW_REDUCED_ACPI | + EFI_ACPI_6_0_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags + NULL_GAS, // GAS ResetReg + 0, // UINT8 ResetValue + EFI_ACPI_6_0_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, + // UINT8 MinorRevision + 0, // UINT64 XFirmwareCtrl + 0, // UINT64 XDsdt + NULL_GAS, // GAS XPm1aEvtBlk + NULL_GAS, // GAS XPm1bEvtBlk + NULL_GAS, // GAS XPm1aCntBlk + NULL_GAS, // GAS XPm1bCntBlk + NULL_GAS, // GAS XPm2CntBlk + NULL_GAS, // GAS XPmTmrBlk + NULL_GAS, // GAS XGpe0Blk + NULL_GAS, // GAS XGpe1Blk + NULL_GAS, // GAS SleepControlReg + NULL_GAS, // GAS SleepStatusReg + 0 // UINT64 HypervisorVendorId +}; + +// +// Reference the table being generated to prevent the optimizer +// from removing the data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Fadt; diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc new file mode 100644 index 0000000000..0053363d11 --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc @@ -0,0 +1,71 @@ +/** @file +* Generic Timer Description Table (GTDT) +* +* Copyright (c) 2012 - 2017, ARM Limited. All rights reserved. +* Copyrignt (c) 2020, Linaro Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include "AcpiTables.h" +#include <Library/AcpiLib.h> +#include <Library/PcdLib.h> +#include <IndustryStandard/Acpi.h> + +#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT +#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0 +#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE +#define GTDT_GLOBAL_FLAGS_LEVEL 0 + +// Note: We could have a build flag that switches between memory mapped/non-memory mapped timer +#ifdef SYSTEM_TIMER_BASE_ADDRESS + #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL) +#else + #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL) + #define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF +#endif + +#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE +#define GTDT_TIMER_LEVEL_TRIGGERED 0 +#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY +#define GTDT_TIMER_ACTIVE_HIGH 0 + +#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED) + + #pragma pack (1) + + typedef struct { + EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; + } GENERIC_TIMER_DESCRIPTION_TABLE; + + #pragma pack () + + GENERIC_TIMER_DESCRIPTION_TABLE Gtdt = { + { + __ACPI_HEADER( + EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, + GENERIC_TIMER_DESCRIPTION_TABLE, + EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION + ), + SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress + 0, // UINT32 Reserved + FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags + FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags + FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags + FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags + 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress + 0, // UINT32 PlatformTimerCount + 0 + }, + }; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Gtdt; diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Madt.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Madt.aslc new file mode 100644 index 0000000000..7bec2d4ef3 --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Madt.aslc @@ -0,0 +1,85 @@ +/** @file +* Multiple APIC Description Table (MADT) +* +* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved. +* Copyright (c) 2018, Linaro Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include <Library/AcpiLib.h> +#include <Library/ArmLib.h> +#include <Library/PcdLib.h> +#include <IndustryStandard/Acpi.h> + +#include "AcpiTables.h" + +#define CORES (FixedPcdGet32 (PcdClusterCount) * \ + FixedPcdGet32 (PcdCoreCount)) +// +// Multiple APIC Description Table +// +#pragma pack (1) + +typedef struct { + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_6_0_GIC_STRUCTURE GicInterfaces[CORES]; + EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; + EFI_ACPI_6_0_GICR_STRUCTURE GicRedistributor; + EFI_ACPI_6_0_GIC_ITS_STRUCTURE GicIts; +} EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE; + +#pragma pack () + +EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { + { + __ACPI_HEADER ( + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE, + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION + ), + // + // MADT specific fields + // + 0, // LocalApicAddress + 0, // Flags + }, + { + // Format: EFI_ACPI_6_0_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags, + // PmuIrq, GicBase, GicVBase, + // GicHBase, GsivId, GicRBase) + // Note: The GIC Structure of the primary CPU must be the first entry + // (see note in 5.2.12.14 GICC Structure of ACPI v6.0). + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-0 + 0, 0, GET_MPID(0, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-0 + 1, 1, GET_MPID(0, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-0 + 2, 2, GET_MPID(0, 2), EFI_ACPI_6_0_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-0 + 3, 3, GET_MPID(0, 3), EFI_ACPI_6_0_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + }, + // GIC Distributor Entry + EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT (0, FixedPcdGet32 (PcdGicDistributorBase), + 0, 3), + // GIC Redistributor + EFI_ACPI_6_0_GIC_REDISTRIBUTOR_INIT (FixedPcdGet32 (PcdGicRedistributorsBase), + 0x300000), + // GIC ITS + EFI_ACPI_6_0_GIC_ITS_FRAME_INIT(0, 0x30020000) +}; + +// +// Reference the table being generated to prevent the optimizer +// from removing the data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Madt; diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc new file mode 100644 index 0000000000..26e1fd3bfe --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc @@ -0,0 +1,50 @@ +/** @file + + ACPI Memory mapped configuration space base address Description Table (MCFG). + Implementation based on PCI Firmware Specification Revision 3.0 final draft, + downloadable at http://www.pcisig.com/home + + Copyright (c) 2014 - 2016, AMD Inc. All rights reserved. + Copyright (c) 2018, Linaro Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <IndustryStandard/Acpi61.h> +#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h> + +#include "AcpiTables.h" + +#pragma pack(push, 1) + +typedef struct { + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header; + EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE Structure[2]; +} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE; + +EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE Mcfg = { + { + __ACPI_HEADER (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE, + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION), + EFI_ACPI_RESERVED_QWORD + }, + { + { + SBSAQEMU_PCI_SEG0_CONFIG_BASE, + 0, + SBSAQEMU_PCI_SEG0_BUSNUM_MIN, + SBSAQEMU_PCI_SEG0_BUSNUM_MAX, + EFI_ACPI_RESERVED_DWORD + } + } +}; + +#pragma pack(pop) + +// +// Reference the table being generated to prevent the optimizer +// from removing the data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Mcfg; diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc new file mode 100644 index 0000000000..fc7098afd1 --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc @@ -0,0 +1,122 @@ +/** @file + + Serial Port Console Redirection Table + (c) 2000 - 2014 Microsoft Corporation. All rights reserved. + http://go.microsoft.com/fwlink/?linkid=403368 + + Copyright (c) 2014 - 2016, AMD Inc. All rights reserved. + Copyright (c) 2018,2020 Linaro Ltd. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <IndustryStandard/Acpi61.h> +#include <IndustryStandard/SerialPortConsoleRedirectionTable.h> + +#include "AcpiTables.h" + +#pragma pack(push, 1) + +STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = { + // + // Header + // + __ACPI_HEADER (EFI_ACPI_5_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE, + 2), /* New MS definition for PL011 support */ + // + // InterfaceType + // + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART, + // + // Reserved[3] + // + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, + // + // BaseAddress + // + { + EFI_ACPI_5_1_SYSTEM_MEMORY, + 32, + 0, + EFI_ACPI_5_1_DWORD, + SBSAQEMU_UART0_BASE + }, + // + // InterruptType + // + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC, + // + // Irq + // + 0, + // + // GlobalSystemInterrupt + // + 33, + // + // BaudRate + // + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200, + // + // Parity + // + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY, + // + // StopBits + // + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1, + // + // FlowControl + // + 0, + // + // TerminalType + // + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI, + // + // Language + // + EFI_ACPI_RESERVED_BYTE, + // + // PciDeviceId + // + 0xFFFF, + // + // PciVendorId + // + 0xFFFF, + // + // PciBusNumber + // + 0x00, + // + // PciDeviceNumber + // + 0x00, + // + // PciFunctionNumber + // + 0x00, + // + // PciFlags + // + 0, + // + // PciSegment + // + 0, + // + // Reserved2 + // + EFI_ACPI_RESERVED_DWORD +}; + +#pragma pack(pop) + +// +// Reference the table being generated to prevent the optimizer from removing +// the data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Spcr; diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c index b7270a07ab..f55dbdb453 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c @@ -51,5 +51,11 @@ InitializeSbsaQemuPlatformDxe ( return Status; } + Status = gBS->InstallMultipleProtocolInterfaces (&ImageHandle, + &gEdkiiPlatformHasAcpiGuid, NULL, NULL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "FAILED TO INSTALL gEDKIIPlatformHasAcpiGuid protocol\n")); + } + return EFI_SUCCESS; } diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf index 21d2135f6d..a50d563782 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf @@ -39,3 +39,13 @@ [Depex] TRUE +[Guids] + gEdkiiPlatformHasAcpiGuid + +[Protocols] + gEdkiiNonDiscoverableDeviceProtocolGuid ## PRODUCES + gEfiAcpiTableProtocolGuid ## CONSUMES + gEfiPciIoProtocolGuid ## CONSUMES + +[FixedPcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision -- 2.28.0

3 years, 9 months

3
8
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Build failed in Jenkins: SBSA QEMU firmware test #8

by ci_notify＠linaro.org

See <https://ci.linaro.org/jenkins/job/ldcg-sbsa-firmware/8/display/redirect> Changes: ------------------------------------------ [...truncated 2.65 MB...] 500K .......... .......... .......... .......... .......... 11.6M 550K .......... .......... .......... .......... .......... 9.05M 600K .......... .......... .......... .......... .......... 11.8M 650K .......... .......... .......... .......... .......... 11.5M 700K .......... .......... .......... .......... .......... 9.70M 750K .......... .......... .......... .......... .......... 9.86M 800K .......... .......... .......... .......... .......... 3.86M 850K .......... .......... .......... .......... .......... 1.57M 900K .......... .......... .......... .......... .......... 11.6M 950K .......... .......... .......... .......... .......... 8.95M 1000K .......... .......... .......... .......... .......... 11.7M 1050K .......... .......... .......... .......... .......... 11.8M 1100K .......... .......... .......... .......... .......... 11.2M 1150K .......... .......... .......... .......... .......... 9.88M 1200K .......... .......... .......... .......... .......... 9.80M 1250K .......... .......... .......... .......... .......... 10.3M 1300K .......... .......... .......... .......... .......... 9.82M 1350K .......... .......... .......... .......... .......... 7.94M 1400K .......... .......... .......... .......... .......... 10.1M 1450K .......... .......... .......... .......... .......... 10.4M 1500K .......... .......... .......... .......... .......... 10.1M 1550K .......... .......... .......... .......... .......... 10.1M 1600K .......... .......... .......... .......... .......... 10.1M 1650K .......... .......... .......... .......... .......... 10.6M 1700K .......... .......... .......... .......... .......... 10.0M 1750K .......... .......... .......... .......... .......... 7.82M 1800K .......... .......... .......... .......... .......... 10.5M 1850K .......... .......... .......... .......... .......... 10.9M 1900K .......... .......... .......... .......... .......... 10.2M 1950K .......... .......... .......... .......... .......... 10.6M 2000K .......... .......... .......... .......... .......... 10.3M 2050K .......... .......... .......... .......... .......... 10.8M 2100K .......... .......... .......... .......... .......... 10.4M 2150K .......... .......... .......... .......... .......... 8.22M 2200K .......... .......... .......... .......... .......... 10.3M 2250K .......... .......... .......... .......... .......... 10.9M 2300K .......... .......... .......... .......... .......... 10.1M 2350K .......... .......... .......... .......... .......... 10.8M 2400K .......... .......... .......... .......... .......... 10.3M 2450K .......... .......... .......... .......... .......... 10.5M 2500K .......... .......... .......... .......... .......... 10.5M 2550K .......... .......... .......... .......... .......... 8.07M 2600K .......... .......... .......... .......... .......... 10.1M 2650K .......... .......... .......... .......... .......... 10.9M 2700K .......... .......... .......... .......... .......... 10.5M 2750K .......... .......... .......... .......... .......... 11.9M 2800K . 3770G=0.6s 2020-08-04 12:59:46 (4.28 MB/s) - ‘v20.03_REL2.4.tar.gz’ saved [2869224] + tar xf v20.03_REL2.4.tar.gz + cp sbsa-acs-20.03_REL2.4/prebuilt_images/v20.03_REL2.4/Sbsa.efi . + truncate -s 16M sda.raw + echo label:gpt + /sbin/sfdisk sda.raw Checking that no-one is using this disk right now ... OK Disk sda.raw: 16 MiB, 16777216 bytes, 32768 sectors Units: sectors of 1 * 512 = 512 bytes Sector size (logical/physical): 512 bytes / 512 bytes I/O size (minimum/optimal): 512 bytes / 512 bytes >>> Script header accepted. >>> Done. Created a new GPT disklabel (GUID: 030CA2C3-8487-8847-83E7-CB50FD59885B). New situation: Disklabel type: gpt Disk identifier: 030CA2C3-8487-8847-83E7-CB50FD59885B The partition table has been altered. Syncing disks. + echo ',,U;' + /sbin/sfdisk sda.raw Checking that no-one is using this disk right now ... OK Disk sda.raw: 16 MiB, 16777216 bytes, 32768 sectors Units: sectors of 1 * 512 = 512 bytes Sector size (logical/physical): 512 bytes / 512 bytes I/O size (minimum/optimal): 512 bytes / 512 bytes Disklabel type: gpt Disk identifier: 030CA2C3-8487-8847-83E7-CB50FD59885B Old situation: >>> Created a new GPT disklabel (GUID: BBA7563A-384D-894F-B12D-67F789F5D11B). sda.raw1: Created a new partition 1 of type 'EFI System' and of size 15 MiB. sda.raw2: Done. New situation: Disklabel type: gpt Disk identifier: BBA7563A-384D-894F-B12D-67F789F5D11B Device Start End Sectors Size Type sda.raw1 2048 32734 30687 15M EFI System The partition table has been altered. Syncing disks. ++ sudo kpartx -avs sda.raw ++ cut '-d ' -f3 + device=loop4p1 + mkdir 1 + sudo mkfs.vfat /dev/mapper/loop4p1 mkfs.fat 4.1 (2017-01-24) + sudo mount /dev/mapper/loop4p1 1 + sudo cp Sbsa.efi 1/ + echo 'fs0:\Sbsa.efi' + sudo tee 1/startup.nsh fs0:\Sbsa.efi + sudo mkdir -p 1/efi/boot/ + sudo cp Build/SbsaQemu/RELEASE_GCC5/AARCH64/Shell.efi 1/efi/boot/bootaa64.efi + sudo umount 1 + sudo kpartx -d sda.raw + timeout 30 ./qemu/aarch64-softmmu/qemu-system-aarch64 -machine sbsa-ref -drive if=pflash,file=SBSA_FLASH0.fd,format=raw -drive if=pflash,file=SBSA_FLASH1.fd,format=raw -drive if=ide,file=sda.raw,format=raw -nographic NOTICE: Booting Trusted Firmware NOTICE: BL1: v2.3(release):v2.3-287-g99c447f44 NOTICE: BL1: Built : 21:08:32, Jul 13 2020 NOTICE: BL1: Booting BL2 NOTICE: BL2: v2.3(release):v2.3-287-g99c447f44 NOTICE: BL2: Built : 21:08:34, Jul 13 2020 NOTICE: BL1: Booting BL31 NOTICE: BL31: v2.3(release):v2.3-287-g99c447f44 NOTICE: BL31: Built : 21:08:36, Jul 13 2020 [2J[04D[=3h[2J[09D[0m[35m[40m[2J[04D[0m[37m[40mUEFI Interactive Shell v2.2 EDK II UEFI v2.70 (EDK II, 0x00010000) [1m[33m[40mMapping table[0m[37m[40m [1m[33m[40m FS0:[0m[37m[40m [1m[37m[40mAlias(s):[0m[37m[40mHD0a65535a1:;BLK1: VenHw(0D51905B-B77E-452A-A2C0-ECA0CC8D514A,000010600000000000)/Sata(0x 0,0xFFFF,0x0)/HD(1,GPT,241385E9-6B88-DE41-BF7D-2DA6B09D4252,0x800,0x77DF) [1m[33m[40m BLK2:[0m[37m[40m [1m[37m[40mAlias(s):[0m[37m[40m VenHw(93E34C7E-B50E-11DF-9223-2443DFD72085,00) [1m[33m[40m BLK0:[0m[37m[40m [1m[37m[40mAlias(s):[0m[37m[40m VenHw(0D51905B-B77E-452A-A2C0-ECA0CC8D514A,000010600000000000)/Sata(0x 0,0xFFFF,0x0) Press [1m[37m[40mESC[0m[37m[40m in 5 seconds to skip [1m[33m[40mstartup.nsh[0m[37m[40m or any other key to continue.[72DPress [1m[37m[40mESC[0m[37m[40m in 4 seconds to skip [1m[33m[40mstartup.nsh[0m[37m[40m or any other key to continue.[72DPress [1m[37m[40mESC[0m[37m[40m in 3 seconds to skip [1m[33m[40mstartup.nsh[0m[37m[40m or any other key to continue.[72DPress [1m[37m[40mESC[0m[37m[40m in 2 seconds to skip [1m[33m[40mstartup.nsh[0m[37m[40m or any other key to continue.[72DPress [1m[37m[40mESC[0m[37m[40m in 1 seconds to skip [1m[33m[40mstartup.nsh[0m[37m[40m or any other key to continue. [1m[33m[40mShell> [0m[37m[40mfs0:\Sbsa.efi SBSA Architecture Compliance Suite Version 2.4 Starting tests for level 4 (Print level is 3) Creating Platform Information Tables PE_INFO: Number of PE detected : 1 GIC_INFO: Number of GICD : 1 GIC_INFO: Number of ITS : 1 TIMER_INFO: Number of system timers : 0 WATCHDOG_INFO: Number of Watchdogs : 0 PCIE_INFO: Number of ECAM regions : 2 SMMU_INFO: Number of SMMU CTRL : 0 Peripheral: Num of USB controllers : 0 Peripheral: Num of SATA controllers : 1 Peripheral: Num of UART controllers : 1 *** Starting PE tests *** 1 : Check for number of PE : Result: PASS 2 : Check for SIMD extensions : Result: PASS 3 : Check for 16-bit ASID support : Result: PASS 4 : Check MMU Granule sizes : Result: PASS 5 : Check Cache Architecture : Result: PASS 6 : Check HW Coherence support : Result: PASS 7 : Check Cryptographic extensions : Result: PASS 8 : Check Little Endian support : Result: PASS 9 : Check EL2 implementation : Result: PASS 10 : Check AARCH64 implementation : Result: PASS 11 : Check PMU Overflow signal : Result: PASS 12 : Check number of PMU counters Failed on PE - 0 for Level= 4 : Result: --FAIL-- 1 13 : Check Synchronous Watchpoints : Result: PASS 14 : Check number of Breakpoints : Result: PASS 15 : Check Arch symmetry across PE Skipping as num of PE is 1 : Result: -SKIPPED- 1 16 : Check EL3 implementation : Result: PASS 17 : Check CRC32 instruction support : Result: PASS 18 : Check for PMBIRQ signal SPE not supported on this PE : Result: -SKIPPED- 1 19 : Check for RAS extension Failed on PE - 0 for Level= 4 : Result: --FAIL-- 1 20 : Check for 16-Bit VMID Failed on PE - 0 for Level= 4 : Result: --FAIL-- 1 21 : Check for Virtual host extensions Failed on PE - 0 for Level= 4 : Result: --FAIL-- 1 22 : Stage 2 control of mem and cache : Result: -SKIPPED- 1 23 : Check for nested virtualization : Result: -SKIPPED- 1 24 : Support Page table map size change: Result: -SKIPPED- 1 25 : Check for pointer signing : Result: -SKIPPED- 1 26 : Check Activity monitors extension : Result: -SKIPPED- 1 27 : Check for SHA3 and SHA512 support : Result: -SKIPPED- 1 *** One or more PE tests have failed... *** *** Starting GIC tests *** 101 : Check GIC version : Result: PASS 102 : If PCIe, then GIC implements ITS : Result: PASS 103 : GIC number of Security states(2) : Result: PASS 104 : GIC Maintenance Interrupt Failed on PE - 0 for Level= 4 : Result: --FAIL-- 1 One or more GIC tests failed. Check Log *** Starting Timer tests *** 201 : Check Counter Frequency : Result: PASS 202 : Check EL0-Phy timer interrupt : Result: PASS 203 : Check EL0-Virtual timer interrupt : Result: PASS 204 : Check EL2-phy timer interrupt : Result: PASS 205 : Check EL2-Virtual timer interrupt v8.1 VHE not supported on this PE : Result: -SKIPPED- 1 206 : SYS Timer if PE Timer not ON PE Timers are not always-on. Failed on PE - 0 for Level= 4 : Result: --FAIL-- 1 207 : CNTCTLBase & CNTBaseN access No System timers are defined : Result: -SKIPPED- 1 *** Skipping remaining System timer tests *** *** One or more tests have Failed/Skipped.*** *** Starting Watchdog tests *** 301 : Check NS Watchdog Accessibility No Watchdogs reported 0 Failed on PE - 0 for Level= 4 : Result: --FAIL-- 1 302 : Check Watchdog WS0 interrupt No Watchdogs reported 0 Failed on PE - 0 for Level= 4 : Result: --FAIL-- 1 ***One or more tests have failed... *** *** Starting PCIe tests *** 401 : Check ECAM Presence : Result: PASS 402 : Check ECAM value in MCFG table : Result: PASS Unexpected exception occured FAR reported = 0x2BDAB180 ESR reported = 0x97800010 ------------------------------------------------------- Total Tests run = 42; Tests Passed = 24 Tests Failed = 8 --------------------------------------------------------- *** SBSA tests complete. Reset the system. *** [1m[33m[40mShell> [0m[37m[40mqemu-system-aarch64: terminating on signal 15 from pid 23553 (timeout) ++ failure_exit ++ cleanup_exit ++ rm -rf /home/buildslave/.docker + cleanup_exit + rm -rf /home/buildslave/.docker Build step 'Execute shell' marked build as failure

3 years, 9 months

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Re: [Asa-dev] [EXTERNAL] [PATCH 4/4] SbsaQemu: Create MADT table at runtime

by Graeme Gregory

Not seeing any issues here assuming previous comments about never creating Madt.aslc in first place are taken. Reviewed-by: Graeme Gregory <graeme(a)nuviainc.com> On 04/08/2020 11:33, Tanmay Jagdale via Asa-dev wrote: > - Added support to create MADT table at runtime. > - Dropped the Madt.aslc from compilation since we are creating > a new one at runtime. > > Signed-off-by: Tanmay Jagdale <tanmay.jagdale(a)linaro.org> > --- > .../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 1 - > .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 158 ++++++++++++++++++ > .../SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 17 +- > 3 files changed, 174 insertions(+), 2 deletions(-) > > diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf > index 9f8ced9db0..571b57c21a 100644 > --- a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf > +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf > @@ -20,7 +20,6 @@ > AcpiTables.h > Dsdt.asl > Fadt.aslc > - Madt.aslc > Gtdt.aslc > Spcr.aslc > Mcfg.aslc > diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c > index 87f2c1aaec..b6acb12f8c 100644 > --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c > +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c > @@ -6,14 +6,23 @@ > * SPDX-License-Identifier: BSD-2-Clause-Patent > * > **/ > +#include <IndustryStandard/Acpi.h> > +#include <IndustryStandard/Acpi10.h> > +#include <IndustryStandard/Acpi60.h> > +#include <Library/AcpiLib.h> > +#include <Library/BaseMemoryLib.h> > #include <Library/DebugLib.h> > +#include <Library/MemoryAllocationLib.h> > #include <Library/PcdLib.h> > #include <Library/UefiBootServicesTableLib.h> > #include <Library/UefiDriverEntryPoint.h> > #include <Library/UefiLib.h> > +#include <Protocol/AcpiTable.h> > #include <Protocol/FdtClient.h> > #include <libfdt.h> > > +#include "../../AcpiTables/AcpiTables.h" > + > /* > * A function that walks through the Device Tree created > * by Qemu and counts the number of CPUs present in it. > @@ -58,6 +67,136 @@ SbsaQemuCountCpusFromFdt( > ASSERT_RETURN_ERROR (PcdStatus); > } > > +/* > + * A Function to Compute the ACPI Table Checksum > + */ > +VOID > +AcpiPlatformChecksum ( > + IN UINT8 *Buffer, > + IN UINTN Size > + ) > +{ > + UINTN ChecksumOffset; > + > + ChecksumOffset = OFFSET_OF (EFI_ACPI_DESCRIPTION_HEADER, Checksum); > + > + // Set checksum to 0 first > + Buffer[ChecksumOffset] = 0; > + > + // Update checksum value > + Buffer[ChecksumOffset] = CalculateCheckSum8(Buffer, Size); > +} > + > +/* > + * A function that add the MADT ACPI table. > + IN EFI_ACPI_COMMON_HEADER *CurrentTable > + */ > +EFI_STATUS > +AddMadtTable ( > + IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable > + ) > +{ > + EFI_STATUS Status; > + UINTN TableHandle; > + UINT32 TableSize; > + EFI_PHYSICAL_ADDRESS PageAddress; > + UINT8 *New; > + UINT32 NumCores; > + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header = { > + __ACPI_HEADER (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, > + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER, > + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION), > + 0, 0 }; > + > + EFI_ACPI_6_0_GIC_STRUCTURE Gicc = EFI_ACPI_6_0_GICC_STRUCTURE_INIT( > + 0, /* GicID */ > + 0, /* AcpiCpuUid */ > + 0, /* Mpidr */ > + EFI_ACPI_6_0_GIC_ENABLED, /* Flags */ > + 23, /* PmuIrq */ > + 0, /* GicBase */ > + 0x2c020000, /* GicVbase */ > + 0x2c010000, /* GicHBase */ > + 25, /* GsivId */ > + 0 /* GicRBase */, > + 0 /* Efficiency */); > + Gicc.PhysicalBaseAddress = FixedPcdGet32 (PcdGicDistributorBase); > + > + EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE Gicd = EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, 0, 0, 3); > + Gicd.PhysicalBaseAddress = FixedPcdGet32 (PcdGicDistributorBase); > + > + EFI_ACPI_6_0_GICR_STRUCTURE Gicr = EFI_ACPI_6_0_GIC_REDISTRIBUTOR_INIT(0, 0x300000); > + Gicr.DiscoveryRangeBaseAddress = FixedPcdGet32 (PcdGicRedistributorsBase); > + > + EFI_ACPI_6_0_GIC_ITS_STRUCTURE GicIts = EFI_ACPI_6_0_GIC_ITS_FRAME_INIT(0, 0x30020000); > + > + NumCores = PcdGet32 (PcdCoreCount); > + > + // Count the new table size based on the number of cores > + TableSize = sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER) + > + (sizeof (EFI_ACPI_6_0_GIC_STRUCTURE) * NumCores) + > + sizeof (EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE) + > + sizeof (EFI_ACPI_6_0_GICR_STRUCTURE) + > + sizeof (EFI_ACPI_6_0_GIC_ITS_STRUCTURE); > + > + PageAddress = 0xFFFFFFFFUL; > + Status = gBS->AllocatePages ( > + AllocateAnyPages, > + EfiACPIReclaimMemory, > + EFI_SIZE_TO_PAGES (TableSize), > + &PageAddress > + ); > + if (EFI_ERROR(Status)) { > + DEBUG((EFI_D_ERROR, "Failed to allocate pages for MADT table\n")); > + return EFI_OUT_OF_RESOURCES; > + } > + > + New = (UINT8 *)(UINTN) PageAddress; > + ZeroMem (New, TableSize); > + > + // Add the ACPI Description table header > + CopyMem(New, &Header, sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER)); > + ((EFI_ACPI_DESCRIPTION_HEADER*) New)->Length = TableSize; > + New += sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER); > + > + // Add new GICC structures for the Cores > + for (NumCores = 0; NumCores < PcdGet32 (PcdCoreCount); NumCores++) { > + EFI_ACPI_6_0_GIC_STRUCTURE *GiccPtr; > + > + CopyMem (New, &Gicc, sizeof (EFI_ACPI_6_0_GIC_STRUCTURE)); > + GiccPtr = (EFI_ACPI_6_0_GIC_STRUCTURE *) New; > + GiccPtr->AcpiProcessorUid = NumCores; > + GiccPtr->MPIDR = NumCores; > + New += sizeof (EFI_ACPI_6_0_GIC_STRUCTURE); > + } > + > + // GIC Distributor Structure > + CopyMem(New, &Gicd, sizeof (EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE)); > + New += sizeof (EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE); > + > + // GIC ReDistributor Structure > + CopyMem(New, &Gicr, sizeof (EFI_ACPI_6_0_GICR_STRUCTURE)); > + New += sizeof (EFI_ACPI_6_0_GICR_STRUCTURE); > + > + // Finally the GIC ITS Structure > + CopyMem(New, &GicIts, sizeof (EFI_ACPI_6_0_GIC_ITS_STRUCTURE)); > + New += sizeof (EFI_ACPI_6_0_GIC_ITS_STRUCTURE); > + > + AcpiPlatformChecksum ((UINT8*) PageAddress, TableSize); > + > + Status = AcpiTable->InstallAcpiTable ( > + AcpiTable, > + (EFI_ACPI_COMMON_HEADER *)PageAddress, > + TableSize, > + &TableHandle > + ); > + if (EFI_ERROR(Status)) { > + DEBUG((EFI_D_ERROR, "Failed to install MADT table\n")); > + } > + > + return Status; > +} > + > EFI_STATUS > EFIAPI > InitializeSbsaQemuAcpiDxe ( > @@ -65,8 +204,27 @@ InitializeSbsaQemuAcpiDxe ( > IN EFI_SYSTEM_TABLE *SystemTable > ) > { > + EFI_STATUS Status; > + EFI_ACPI_TABLE_PROTOCOL *AcpiTable; > + > // Parse the device tree and get the number of CPUs > SbsaQemuCountCpusFromFdt(); > > + // Check if ACPI Table Protocol has been installed > + Status = gBS->LocateProtocol ( > + &gEfiAcpiTableProtocolGuid, > + NULL, > + (VOID **)&AcpiTable > + ); > + if (EFI_ERROR (Status)) { > + DEBUG ((EFI_D_ERROR, "Failed to locate ACPI Table Protocol\n")); > + return Status; > + } > + > + Status = AddMadtTable (AcpiTable); > + if (EFI_ERROR(Status)) { > + DEBUG((EFI_D_ERROR, "Failed to add MADT table\n")); > + } > + > return EFI_SUCCESS; > } > diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf > index efc4d295bf..fc1d25e7fe 100644 > --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf > +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf > @@ -41,9 +41,24 @@ > UefiRuntimeServicesTableLib > > [Pcd] > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile > gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount > gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount > gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress > > [Depex] > - TRUE > + gEfiAcpiTableProtocolGuid ## CONSUMES > + > +[Guids] > + gEdkiiPlatformHasAcpiGuid > + > +[Protocols] > + gEfiAcpiTableProtocolGuid ## CONSUMES > + > +[FixedPcd] > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision > + gArmTokenSpaceGuid.PcdGicDistributorBase > + gArmTokenSpaceGuid.PcdGicRedistributorsBase > + > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision

3 years, 9 months

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Re: [Asa-dev] [EXTERNAL] [PATCH 3/4] SbsaQemu: Add new ACPI driver and FDT parser to count CPU

by Graeme Gregory

On 04/08/2020 11:33, Tanmay Jagdale via Asa-dev wrote: > - Add a new ACPI driver for the SbsaQemu platform which would > handle any modifications needed for the static ACPI tables. > > - Added a parser function in this driver which parses the FDT > created by Qemu to determine the number of CPUs and hence > update the PcdCoreCount variable. > > Signed-off-by: Tanmay Jagdale <tanmay.jagdale(a)linaro.org> > --- > Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 9 ++- > Platform/Qemu/SbsaQemu/SbsaQemu.fdf | 7 +- > Silicon/Qemu/SbsaQemu/Acpi.dsc.inc | 10 +-- > .../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 2 - > Silicon/Qemu/SbsaQemu/AcpiTables/Madt.aslc | 4 +- > .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 72 +++++++++++++++++++ > .../SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 49 +++++++++++++ > .../SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c | 6 -- > .../SbsaQemuPlatformDxe.inf | 7 -- > Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 4 ++ > 10 files changed, 134 insertions(+), 36 deletions(-) > create mode 100644 Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c > create mode 100644 Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf > > diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc > index ac1398af8f..d42b9cd4de 100644 > --- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc > +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc > @@ -75,6 +75,7 @@ DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE > ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf > FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf > > + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf > UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf > OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf > > @@ -217,7 +218,6 @@ DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE > > PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf > > - FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf > ArmPlatformLib|Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuLib.inf > > [LibraryClasses.common.DXE_CORE] > @@ -300,10 +300,6 @@ DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE > gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0 > gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320 > > - # Core and Cluster Count > - gArmPlatformTokenSpaceGuid.PcdCoreCount|4 > - gArmPlatformTokenSpaceGuid.PcdClusterCount|1 > - > # DEBUG_ASSERT_ENABLED 0x01 > # DEBUG_PRINT_ENABLED 0x02 > # DEBUG_CODE_ENABLED 0x04 > @@ -480,6 +476,9 @@ DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE > [PcdsDynamicDefault.common] > gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3 > > + # Core and Cluster Count > + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount|1 > + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount|1 > > # System Memory Size -- 128 MB initially, actual size will be fetched from DT > # TODO as no DT will be used we should pass this by some other method > diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf b/Platform/Qemu/SbsaQemu/SbsaQemu.fdf > index 7f1a60e3ee..3bcf0bf004 100644 > --- a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf > +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.fdf > @@ -232,6 +232,7 @@ READ_LOCK_STATUS = TRUE > # > INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf > INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf > + INF Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf > INF RuleOverride = ACPITABLE Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf > INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf > > @@ -309,9 +310,3 @@ READ_LOCK_STATUS = TRUE > } > > !include ArmVirtPkg/ArmVirtRules.fdf.inc > - > -[Rule.Common.USER_DEFINED.ACPITABLE] > - FILE FREEFORM = $(NAMED_GUID) { > - RAW ACPI |.acpi > - RAW ASL |.aml > - } Unrelated change that has snuck in? > diff --git a/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc b/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc > index 76d0fac079..c3e910763c 100644 > --- a/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc > +++ b/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc > @@ -30,13 +30,7 @@ > # > # ACPI support > # > - MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf { > - <LibraryClasses> > - NULL|EmbeddedPkg/Library/PlatformHasAcpiLib/PlatformHasAcpiLib.inf > - > - <PcdsFixedAtBuild> > - # support ACPI v5.0 or later > - gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20 > - } > + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf > MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf > Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf > + Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf > diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf > index 63d5754e16..9f8ced9db0 100644 > --- a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf > +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf > @@ -33,8 +33,6 @@ > MdeModulePkg/MdeModulePkg.dec > > [FixedPcd] > - gArmPlatformTokenSpaceGuid.PcdClusterCount > - gArmPlatformTokenSpaceGuid.PcdCoreCount > gArmTokenSpaceGuid.PcdGicDistributorBase > gArmTokenSpaceGuid.PcdGicRedistributorsBase > > diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Madt.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Madt.aslc > index 7bec2d4ef3..9e39e2e139 100644 > --- a/Silicon/Qemu/SbsaQemu/AcpiTables/Madt.aslc > +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Madt.aslc > @@ -15,8 +15,8 @@ > > #include "AcpiTables.h" > > -#define CORES (FixedPcdGet32 (PcdClusterCount) * \ > - FixedPcdGet32 (PcdCoreCount)) > +#define CORES 4 > + > // > // Multiple APIC Description Table > // This seems to be purely needed because patch 1 created this file and as I commented in patch 1 I don't think we need it. Graeme > diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c > new file mode 100644 > index 0000000000..87f2c1aaec > --- /dev/null > +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c > @@ -0,0 +1,72 @@ > +/** @file > +* This file is an ACPI driver for the Qemu SBSA platform. > +* > +* Copyright (c) 2020, Linaro Ltd. All rights reserved. > +* > +* SPDX-License-Identifier: BSD-2-Clause-Patent > +* > +**/ > +#include <Library/DebugLib.h> > +#include <Library/PcdLib.h> > +#include <Library/UefiBootServicesTableLib.h> > +#include <Library/UefiDriverEntryPoint.h> > +#include <Library/UefiLib.h> > +#include <Protocol/FdtClient.h> > +#include <libfdt.h> > + > +/* > + * A function that walks through the Device Tree created > + * by Qemu and counts the number of CPUs present in it. > + */ > +VOID > +SbsaQemuCountCpusFromFdt( > + VOID > +) > +{ > + VOID *DeviceTreeBase; > + INT32 Node, Prev; > + RETURN_STATUS PcdStatus; > + INT32 CpuNode; > + INT32 CpuCount; > + > + DeviceTreeBase = (VOID *)(UINTN)PcdGet64 (PcdDeviceTreeBaseAddress); > + ASSERT (DeviceTreeBase != NULL); > + > + // Make sure we have a valid device tree blob > + ASSERT (fdt_check_header (DeviceTreeBase) == 0); > + > + CpuNode = fdt_path_offset (DeviceTreeBase, "/cpus"); > + if (CpuNode <= 0) { > + DEBUG((EFI_D_ERROR, "Unable to locate /cpus in device tree\n")); > + return; > + } > + > + CpuCount = 0; > + > + // Walk through /cpus node and count the number of subnodes. > + // The count of these subnodes corresponds to the numer of > + // CPUs created by Qemu. > + for (Prev = fdt_first_subnode(DeviceTreeBase, CpuNode);; Prev = Node) { > + CpuCount++; > + Node = fdt_next_subnode (DeviceTreeBase, Prev); > + if (Node < 0) { > + break; > + } > + } > + > + PcdStatus = PcdSet32S (PcdCoreCount, CpuCount); > + ASSERT_RETURN_ERROR (PcdStatus); > +} > + > +EFI_STATUS > +EFIAPI > +InitializeSbsaQemuAcpiDxe ( > + IN EFI_HANDLE ImageHandle, > + IN EFI_SYSTEM_TABLE *SystemTable > + ) > +{ > + // Parse the device tree and get the number of CPUs > + SbsaQemuCountCpusFromFdt(); > + > + return EFI_SUCCESS; > +} > diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf > new file mode 100644 > index 0000000000..efc4d295bf > --- /dev/null > +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf > @@ -0,0 +1,49 @@ > +## @file > +# This driver modifies ACPI tables for the Qemu SBSA platform > +# > +# Copyright (c) 2020, Linaro Ltd. All rights reserved. > +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +[Defines] > + INF_VERSION = 0x0001001d > + BASE_NAME = SbsaQemuAcpiDxe > + FILE_GUID = 6c592dc9-76c8-474f-93b2-bf1e8f15ae35 > + MODULE_TYPE = DXE_DRIVER > + VERSION_STRING = 1.0 > + > + ENTRY_POINT = InitializeSbsaQemuAcpiDxe > + > +[Sources] > + SbsaQemuAcpiDxe.c > + > +[Packages] > + ArmPkg/ArmPkg.dec > + ArmPlatformPkg/ArmPlatformPkg.dec > + ArmVirtPkg/ArmVirtPkg.dec > + EmbeddedPkg/EmbeddedPkg.dec > + MdeModulePkg/MdeModulePkg.dec > + MdePkg/MdePkg.dec > + Silicon/Qemu/SbsaQemu/SbsaQemu.dec > + > +[LibraryClasses] > + ArmLib > + BaseMemoryLib > + DebugLib > + BaseLib > + FdtLib > + DxeServicesLib > + PcdLib > + UefiDriverEntryPoint > + UefiLib > + UefiRuntimeServicesTableLib > + > +[Pcd] > + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount > + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount > + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress > + > +[Depex] > + TRUE > diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c > index f55dbdb453..b7270a07ab 100644 > --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c > +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c > @@ -51,11 +51,5 @@ InitializeSbsaQemuPlatformDxe ( > return Status; > } > > - Status = gBS->InstallMultipleProtocolInterfaces (&ImageHandle, > - &gEdkiiPlatformHasAcpiGuid, NULL, NULL); > - if (EFI_ERROR (Status)) { > - DEBUG ((DEBUG_ERROR, "FAILED TO INSTALL gEDKIIPlatformHasAcpiGuid protocol\n")); > - } > - > return EFI_SUCCESS; > } > diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf > index a50d563782..6c9c28946e 100644 > --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf > +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf > @@ -39,13 +39,6 @@ > [Depex] > TRUE > > -[Guids] > - gEdkiiPlatformHasAcpiGuid > - > [Protocols] > gEdkiiNonDiscoverableDeviceProtocolGuid ## PRODUCES > - gEfiAcpiTableProtocolGuid ## CONSUMES > gEfiPciIoProtocolGuid ## CONSUMES > - > -[FixedPcd] > - gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision > diff --git a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec > index cd879f4dbd..6aca632996 100644 > --- a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec > +++ b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec > @@ -35,3 +35,7 @@ > gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciBase|0|UINT64|0x00000003 > gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciSize|0x10000|UINT32|0x00000004 > gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress|0x10000000000|UINT64|0x00000005 > + > +[PcdsDynamic.common] > + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount|0x1|UINT32|0x00000006 > + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount|0x1|UINT32|0x00000007

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Re: [Asa-dev] [EXTERNAL] [PATCH 2/4] SbsaQemu: Use macros for the PCI entries in DSDT

by Graeme Gregory

On 04/08/2020 11:33, Tanmay Jagdale via Asa-dev wrote: > Signed-off-by: Tanmay Jagdale <tanmay.jagdale(a)linaro.org> > --- > Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 1294 +++------------------ > 1 file changed, 180 insertions(+), 1114 deletions(-) > > diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl > index d63e22dd6b..0323657512 100644 > --- a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl > +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl > @@ -10,6 +10,23 @@ > > #include "AcpiTables.h" > > +#define LINK_DEVICE(Uid, LinkName, Irq) \ > + Device(LinkName) { \ > + Name(_HID, EISAID("PNP0C0F")) \ > + Name(_UID, Uid) \ > + Name(_PRS, ResourceTemplate() { \ > + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { Irq } \ > + }) \ > + Method (_CRS, 0) { Return (_PRS) } \ > + Method (_SRS, 1) { } \ > + Method (_DIS) { } \ > + } > + > +#define PRT_ENTRY(Address, Pin, Link) \ > + Package (4) { \ > + Address, Pin, Link, Zero \ > + } > + > DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LNRO", "SBSA", > EFI_ACPI_OEM_REVISION) { > Scope (_SB) { > @@ -158,1123 +175,172 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LNRO", "SBSA", > return (0xf0000000) > } > > - Device (GSI0) > - { > - Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID > - Name (_UID, Zero) // _UID: Unique ID > - Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings > - { > - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) > - { > - 0x00000023, > - } > - }) > - Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > - { > - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) > - { > - 0x00000023, > - } > - }) > - Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings > - { > - } > - } > - > - Device (GSI1) > - { > - Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID > - Name (_UID, Zero) // _UID: Unique ID > - Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings > - { > - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) > - { > - 0x00000024, > - } > - }) > - Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > - { > - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) > - { > - 0x00000024, > - } > - }) > - Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings > - { > - } > - } > - > - Device (GSI2) > - { > - Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID > - Name (_UID, Zero) // _UID: Unique ID > - Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings > - { > - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) > - { > - 0x00000025, > - } > - }) > - Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > - { > - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) > - { > - 0x00000025, > - } > - }) > - Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings > - { > - } > - } > - > - Device (GSI3) > - { > - Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID > - Name (_UID, Zero) // _UID: Unique ID > - Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings > - { > - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) > - { > - 0x00000026, > - } > - }) > - Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings > - { > - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) > - { > - 0x00000026, > - } > - }) > - Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings > - { > - } > - } > + LINK_DEVICE(0, GSI0, 0x23) > + LINK_DEVICE(1, GSI1, 0x24) > + LINK_DEVICE(2, GSI2, 0x25) > + LINK_DEVICE(3, GSI3, 0x26) This is much better, but rather than deleting from DSDT added in patch 1, just remove the old PCI from patch 1 DSDT and just make this patch add the new stuff. This comment for below too. Graeme > > Name (_PRT, Package () // _PRT: PCI Routing Table > { > - Package () > - { > - 0x0000FFFF, > - Zero, > - GSI0, > - Zero > - }, > - > - Package () > - { > - 0x0000FFFF, > - Zero, > - GSI1, > - Zero > - }, > - > - Package () > - { > - 0x0000FFFF, > - Zero, > - GSI2, > - Zero > - }, > - > - Package () > - { > - 0x0000FFFF, > - Zero, > - GSI3, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0001FFFF, > - Zero, > - GSI1, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0001FFFF, > - One, > - GSI2, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0001FFFF, > - 0x02, > - GSI3, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0001FFFF, > - 0x03, > - GSI0, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0002FFFF, > - Zero, > - GSI2, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0002FFFF, > - One, > - GSI3, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0002FFFF, > - 0x02, > - GSI0, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0002FFFF, > - 0x03, > - GSI1, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0003FFFF, > - Zero, > - GSI3, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0003FFFF, > - One, > - GSI0, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0003FFFF, > - 0x02, > - GSI1, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0003FFFF, > - 0x03, > - GSI2, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0004FFFF, > - Zero, > - GSI0, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0004FFFF, > - One, > - GSI1, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0004FFFF, > - 0x02, > - GSI2, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0004FFFF, > - 0x03, > - GSI3, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0005FFFF, > - Zero, > - GSI1, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0005FFFF, > - One, > - GSI2, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0005FFFF, > - 0x02, > - GSI3, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0005FFFF, > - 0x03, > - GSI0, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0006FFFF, > - Zero, > - GSI2, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0006FFFF, > - One, > - GSI3, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0006FFFF, > - 0x02, > - GSI0, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0006FFFF, > - 0x03, > - GSI1, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0007FFFF, > - Zero, > - GSI3, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0007FFFF, > - One, > - GSI0, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0007FFFF, > - 0x02, > - GSI1, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0007FFFF, > - 0x03, > - GSI2, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0008FFFF, > - Zero, > - GSI0, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0008FFFF, > - One, > - GSI1, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0008FFFF, > - 0x02, > - GSI2, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0008FFFF, > - 0x03, > - GSI3, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0009FFFF, > - Zero, > - GSI1, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0009FFFF, > - One, > - GSI2, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0009FFFF, > - 0x02, > - GSI3, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0009FFFF, > - 0x03, > - GSI0, > - Zero > - }, > - > - Package (0x04) > - { > - 0x000AFFFF, > - Zero, > - GSI2, > - Zero > - }, > - > - Package (0x04) > - { > - 0x000AFFFF, > - One, > - GSI3, > - Zero > - }, > - > - Package (0x04) > - { > - 0x000AFFFF, > - 0x02, > - GSI0, > - Zero > - }, > - > - Package (0x04) > - { > - 0x000AFFFF, > - 0x03, > - GSI1, > - Zero > - }, > - > - Package (0x04) > - { > - 0x000BFFFF, > - Zero, > - GSI3, > - Zero > - }, > - > - Package (0x04) > - { > - 0x000BFFFF, > - One, > - GSI0, > - Zero > - }, > - > - Package (0x04) > - { > - 0x000BFFFF, > - 0x02, > - GSI1, > - Zero > - }, > - > - Package (0x04) > - { > - 0x000BFFFF, > - 0x03, > - GSI2, > - Zero > - }, > - > - Package (0x04) > - { > - 0x000CFFFF, > - Zero, > - GSI0, > - Zero > - }, > - > - Package (0x04) > - { > - 0x000CFFFF, > - One, > - GSI1, > - Zero > - }, > - > - Package (0x04) > - { > - 0x000CFFFF, > - 0x02, > - GSI2, > - Zero > - }, > - > - Package (0x04) > - { > - 0x000CFFFF, > - 0x03, > - GSI3, > - Zero > - }, > - > - Package (0x04) > - { > - 0x000DFFFF, > - Zero, > - GSI1, > - Zero > - }, > - > - Package (0x04) > - { > - 0x000DFFFF, > - One, > - GSI2, > - Zero > - }, > - > - Package (0x04) > - { > - 0x000DFFFF, > - 0x02, > - GSI3, > - Zero > - }, > - > - Package (0x04) > - { > - 0x000DFFFF, > - 0x03, > - GSI0, > - Zero > - }, > - > - Package (0x04) > - { > - 0x000EFFFF, > - Zero, > - GSI2, > - Zero > - }, > - > - Package (0x04) > - { > - 0x000EFFFF, > - One, > - GSI3, > - Zero > - }, > - > - Package (0x04) > - { > - 0x000EFFFF, > - 0x02, > - GSI0, > - Zero > - }, > - > - Package (0x04) > - { > - 0x000EFFFF, > - 0x03, > - GSI1, > - Zero > - }, > - > - Package (0x04) > - { > - 0x000FFFFF, > - Zero, > - GSI3, > - Zero > - }, > - > - Package (0x04) > - { > - 0x000FFFFF, > - One, > - GSI0, > - Zero > - }, > - > - Package (0x04) > - { > - 0x000FFFFF, > - 0x02, > - GSI1, > - Zero > - }, > - > - Package (0x04) > - { > - 0x000FFFFF, > - 0x03, > - GSI2, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0010FFFF, > - Zero, > - GSI0, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0010FFFF, > - One, > - GSI1, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0010FFFF, > - 0x02, > - GSI2, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0010FFFF, > - 0x03, > - GSI3, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0011FFFF, > - Zero, > - GSI1, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0011FFFF, > - One, > - GSI2, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0011FFFF, > - 0x02, > - GSI3, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0011FFFF, > - 0x03, > - GSI0, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0012FFFF, > - Zero, > - GSI2, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0012FFFF, > - One, > - GSI3, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0012FFFF, > - 0x02, > - GSI0, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0012FFFF, > - 0x03, > - GSI1, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0013FFFF, > - Zero, > - GSI3, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0013FFFF, > - One, > - GSI0, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0013FFFF, > - 0x02, > - GSI1, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0013FFFF, > - 0x03, > - GSI2, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0014FFFF, > - Zero, > - GSI0, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0014FFFF, > - One, > - GSI1, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0014FFFF, > - 0x02, > - GSI2, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0014FFFF, > - 0x03, > - GSI3, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0015FFFF, > - Zero, > - GSI1, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0015FFFF, > - One, > - GSI2, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0015FFFF, > - 0x02, > - GSI3, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0015FFFF, > - 0x03, > - GSI0, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0016FFFF, > - Zero, > - GSI2, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0016FFFF, > - One, > - GSI3, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0016FFFF, > - 0x02, > - GSI0, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0016FFFF, > - 0x03, > - GSI1, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0017FFFF, > - Zero, > - GSI3, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0017FFFF, > - One, > - GSI0, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0017FFFF, > - 0x02, > - GSI1, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0017FFFF, > - 0x03, > - GSI2, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0018FFFF, > - Zero, > - GSI0, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0018FFFF, > - One, > - GSI1, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0018FFFF, > - 0x02, > - GSI2, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0018FFFF, > - 0x03, > - GSI3, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0019FFFF, > - Zero, > - GSI1, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0019FFFF, > - One, > - GSI2, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0019FFFF, > - 0x02, > - GSI3, > - Zero > - }, > - > - Package (0x04) > - { > - 0x0019FFFF, > - 0x03, > - GSI0, > - Zero > - }, > - > - Package (0x04) > - { > - 0x001AFFFF, > - Zero, > - GSI2, > - Zero > - }, > - > - Package (0x04) > - { > - 0x001AFFFF, > - One, > - GSI3, > - Zero > - }, > - > - Package (0x04) > - { > - 0x001AFFFF, > - 0x02, > - GSI0, > - Zero > - }, > - > - Package (0x04) > - { > - 0x001AFFFF, > - 0x03, > - GSI1, > - Zero > - }, > - > - Package (0x04) > - { > - 0x001BFFFF, > - Zero, > - GSI3, > - Zero > - }, > - > - Package (0x04) > - { > - 0x001BFFFF, > - One, > - GSI0, > - Zero > - }, > - > - Package (0x04) > - { > - 0x001BFFFF, > - 0x02, > - GSI1, > - Zero > - }, > - > - Package (0x04) > - { > - 0x001BFFFF, > - 0x03, > - GSI2, > - Zero > - }, > - > - Package (0x04) > - { > - 0x001CFFFF, > - Zero, > - GSI0, > - Zero > - }, > - > - Package (0x04) > - { > - 0x001CFFFF, > - One, > - GSI1, > - Zero > - }, > - > - Package (0x04) > - { > - 0x001CFFFF, > - 0x02, > - GSI2, > - Zero > - }, > - > - Package (0x04) > - { > - 0x001CFFFF, > - 0x03, > - GSI3, > - Zero > - }, > - > - Package (0x04) > - { > - 0x001DFFFF, > - Zero, > - GSI1, > - Zero > - }, > - > - Package (0x04) > - { > - 0x001DFFFF, > - One, > - GSI2, > - Zero > - }, > - > - Package (0x04) > - { > - 0x001DFFFF, > - 0x02, > - GSI3, > - Zero > - }, > - > - Package (0x04) > - { > - 0x001DFFFF, > - 0x03, > - GSI0, > - Zero > - }, > - > - Package (0x04) > - { > - 0x001EFFFF, > - Zero, > - GSI2, > - Zero > - }, > - > - Package (0x04) > - { > - 0x001EFFFF, > - One, > - GSI3, > - Zero > - }, > - > - Package (0x04) > - { > - 0x001EFFFF, > - 0x02, > - GSI0, > - Zero > - }, > - > - Package (0x04) > - { > - 0x001EFFFF, > - 0x03, > - GSI1, > - Zero > - }, > - > - Package (0x04) > - { > - 0x001FFFFF, > - Zero, > - GSI3, > - Zero > - }, > - > - Package (0x04) > - { > - 0x001FFFFF, > - One, > - GSI0, > - Zero > - }, > - > - Package (0x04) > - { > - 0x001FFFFF, > - 0x02, > - GSI1, > - Zero > - }, > - > - Package (0x04) > - { > - 0x001FFFFF, > - 0x03, > - GSI2, > - Zero > - }, > + PRT_ENTRY(0x0000FFFF, 0, GSI0), > + PRT_ENTRY(0x0000FFFF, 0, GSI1), > + PRT_ENTRY(0x0000FFFF, 0, GSI2), > + PRT_ENTRY(0x0000FFFF, 0, GSI3), > + > + PRT_ENTRY(0x0001FFFF, 0, GSI1), > + PRT_ENTRY(0x0001FFFF, 1, GSI2), > + PRT_ENTRY(0x0001FFFF, 2, GSI3), > + PRT_ENTRY(0x0001FFFF, 3, GSI0), > + > + PRT_ENTRY(0x0002FFFF, 0, GSI2), > + PRT_ENTRY(0x0002FFFF, 1, GSI3), > + PRT_ENTRY(0x0002FFFF, 2, GSI0), > + PRT_ENTRY(0x0002FFFF, 3, GSI1), > + > + PRT_ENTRY(0x0003FFFF, 0, GSI3), > + PRT_ENTRY(0x0003FFFF, 1, GSI0), > + PRT_ENTRY(0x0003FFFF, 2, GSI1), > + PRT_ENTRY(0x0003FFFF, 3, GSI2), > + > + PRT_ENTRY(0x0004FFFF, 0, GSI0), > + PRT_ENTRY(0x0004FFFF, 1, GSI1), > + PRT_ENTRY(0x0004FFFF, 2, GSI2), > + PRT_ENTRY(0x0004FFFF, 3, GSI3), > + > + PRT_ENTRY(0x0005FFFF, 0, GSI1), > + PRT_ENTRY(0x0005FFFF, 1, GSI2), > + PRT_ENTRY(0x0005FFFF, 2, GSI3), > + PRT_ENTRY(0x0005FFFF, 3, GSI0), > + > + PRT_ENTRY(0x0006FFFF, 0, GSI2), > + PRT_ENTRY(0x0006FFFF, 1, GSI3), > + PRT_ENTRY(0x0006FFFF, 2, GSI0), > + PRT_ENTRY(0x0006FFFF, 3, GSI1), > + > + PRT_ENTRY(0x0007FFFF, 0, GSI3), > + PRT_ENTRY(0x0007FFFF, 1, GSI0), > + PRT_ENTRY(0x0007FFFF, 2, GSI1), > + PRT_ENTRY(0x0007FFFF, 3, GSI2), > + > + PRT_ENTRY(0x0008FFFF, 0, GSI0), > + PRT_ENTRY(0x0008FFFF, 1, GSI1), > + PRT_ENTRY(0x0008FFFF, 2, GSI2), > + PRT_ENTRY(0x0008FFFF, 3, GSI3), > + > + PRT_ENTRY(0x0009FFFF, 0, GSI1), > + PRT_ENTRY(0x0009FFFF, 1, GSI2), > + PRT_ENTRY(0x0009FFFF, 2, GSI3), > + PRT_ENTRY(0x0009FFFF, 3, GSI0), > + > + PRT_ENTRY(0x000AFFFF, 0, GSI2), > + PRT_ENTRY(0x000AFFFF, 1, GSI3), > + PRT_ENTRY(0x000AFFFF, 2, GSI0), > + PRT_ENTRY(0x000AFFFF, 3, GSI1), > + > + PRT_ENTRY(0x000BFFFF, 0, GSI3), > + PRT_ENTRY(0x000BFFFF, 1, GSI0), > + PRT_ENTRY(0x000BFFFF, 2, GSI1), > + PRT_ENTRY(0x000BFFFF, 3, GSI2), > + > + PRT_ENTRY(0x000CFFFF, 0, GSI0), > + PRT_ENTRY(0x000CFFFF, 1, GSI1), > + PRT_ENTRY(0x000CFFFF, 2, GSI2), > + PRT_ENTRY(0x000CFFFF, 3, GSI3), > + > + PRT_ENTRY(0x000DFFFF, 0, GSI1), > + PRT_ENTRY(0x000DFFFF, 1, GSI2), > + PRT_ENTRY(0x000DFFFF, 2, GSI3), > + PRT_ENTRY(0x000DFFFF, 3, GSI0), > + > + PRT_ENTRY(0x000EFFFF, 0, GSI2), > + PRT_ENTRY(0x000EFFFF, 1, GSI3), > + PRT_ENTRY(0x000EFFFF, 2, GSI0), > + PRT_ENTRY(0x000EFFFF, 3, GSI1), > + > + PRT_ENTRY(0x000FFFFF, 0, GSI3), > + PRT_ENTRY(0x000FFFFF, 1, GSI0), > + PRT_ENTRY(0x000FFFFF, 2, GSI1), > + PRT_ENTRY(0x000FFFFF, 3, GSI2), > + > + PRT_ENTRY(0x0010FFFF, 0, GSI0), > + PRT_ENTRY(0x0010FFFF, 1, GSI1), > + PRT_ENTRY(0x0010FFFF, 2, GSI2), > + PRT_ENTRY(0x0010FFFF, 3, GSI3), > + > + PRT_ENTRY(0x0011FFFF, 0, GSI1), > + PRT_ENTRY(0x0011FFFF, 1, GSI2), > + PRT_ENTRY(0x0011FFFF, 2, GSI3), > + PRT_ENTRY(0x0011FFFF, 3, GSI0), > + > + PRT_ENTRY(0x0012FFFF, 0, GSI2), > + PRT_ENTRY(0x0012FFFF, 1, GSI3), > + PRT_ENTRY(0x0012FFFF, 2, GSI0), > + PRT_ENTRY(0x0012FFFF, 3, GSI1), > + > + PRT_ENTRY(0x0013FFFF, 0, GSI3), > + PRT_ENTRY(0x0013FFFF, 1, GSI0), > + PRT_ENTRY(0x0013FFFF, 2, GSI1), > + PRT_ENTRY(0x0013FFFF, 3, GSI2), > + > + PRT_ENTRY(0x0014FFFF, 0, GSI0), > + PRT_ENTRY(0x0014FFFF, 1, GSI1), > + PRT_ENTRY(0x0014FFFF, 2, GSI2), > + PRT_ENTRY(0x0014FFFF, 3, GSI3), > + > + PRT_ENTRY(0x0015FFFF, 0, GSI1), > + PRT_ENTRY(0x0015FFFF, 1, GSI2), > + PRT_ENTRY(0x0015FFFF, 2, GSI3), > + PRT_ENTRY(0x0015FFFF, 3, GSI0), > + > + PRT_ENTRY(0x0016FFFF, 0, GSI2), > + PRT_ENTRY(0x0016FFFF, 1, GSI3), > + PRT_ENTRY(0x0016FFFF, 2, GSI0), > + PRT_ENTRY(0x0016FFFF, 3, GSI1), > + > + PRT_ENTRY(0x0017FFFF, 0, GSI3), > + PRT_ENTRY(0x0017FFFF, 1, GSI0), > + PRT_ENTRY(0x0017FFFF, 2, GSI1), > + PRT_ENTRY(0x0017FFFF, 3, GSI2), > + > + PRT_ENTRY(0x0018FFFF, 0, GSI0), > + PRT_ENTRY(0x0018FFFF, 1, GSI1), > + PRT_ENTRY(0x0018FFFF, 2, GSI2), > + PRT_ENTRY(0x0018FFFF, 3, GSI3), > + > + PRT_ENTRY(0x0019FFFF, 0, GSI1), > + PRT_ENTRY(0x0019FFFF, 1, GSI2), > + PRT_ENTRY(0x0019FFFF, 2, GSI3), > + PRT_ENTRY(0x0019FFFF, 3, GSI0), > + > + PRT_ENTRY(0x001AFFFF, 0, GSI2), > + PRT_ENTRY(0x001AFFFF, 1, GSI3), > + PRT_ENTRY(0x001AFFFF, 2, GSI0), > + PRT_ENTRY(0x001AFFFF, 3, GSI1), > + > + PRT_ENTRY(0x001BFFFF, 0, GSI3), > + PRT_ENTRY(0x001BFFFF, 1, GSI0), > + PRT_ENTRY(0x001BFFFF, 2, GSI1), > + PRT_ENTRY(0x001BFFFF, 3, GSI2), > + > + PRT_ENTRY(0x001CFFFF, 0, GSI0), > + PRT_ENTRY(0x001CFFFF, 1, GSI1), > + PRT_ENTRY(0x001CFFFF, 2, GSI2), > + PRT_ENTRY(0x001CFFFF, 3, GSI3), > + > + PRT_ENTRY(0x001DFFFF, 0, GSI1), > + PRT_ENTRY(0x001DFFFF, 1, GSI2), > + PRT_ENTRY(0x001DFFFF, 2, GSI3), > + PRT_ENTRY(0x001DFFFF, 3, GSI0), > + > + PRT_ENTRY(0x001EFFFF, 0, GSI2), > + PRT_ENTRY(0x001EFFFF, 1, GSI3), > + PRT_ENTRY(0x001EFFFF, 2, GSI0), > + PRT_ENTRY(0x001EFFFF, 3, GSI1), > + > + PRT_ENTRY(0x001FFFFF, 0, GSI3), > + PRT_ENTRY(0x001FFFFF, 1, GSI0), > + PRT_ENTRY(0x001FFFFF, 2, GSI1), > + PRT_ENTRY(0x001FFFFF, 3, GSI2), > }) > > // Root complex resources

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