See <https://ci.linaro.org/jenkins/job/ldcg-sbsa-firmware/14/display/redirect>
Changes:
------------------------------------------
[...truncated 2.76 MB...]
NOTICE: BL1: Booting BL31
NOTICE: BL31: v2.3(release):v2.3-673-g332d194fd
NOTICE: BL31: Built : 13:33:00, Sep 15 2020
[2J[04D[=3h[2J[09D[0m[35m[40m[0m[30m[47mWelcome to GRUB!
[0m[37m[40merror: no such device: ((hd0,gpt2)/EFI/BOOT)/EFI/BOOT/grub.cfg.
[0m[30m[40m[2J[01;01H[0m[37m[40m[02;30HGNU GRUB version 2.02
[01C/----------------------------------------------------------------------------\[05;02H|[76C|[06;02H|[76C|[07;02H|[76C|[08;02H|[76C|[09;02H|[76C|[10;02H|[76C|[11;02H|[76C|[12;02H|[76C|[13;02H|[76C|[14;02H|[76C|[15;02H|[76C|[16;02H|[76C|[17;02H|[76C|[18;02H\----------------------------------------------------------------------------/[19;02H[20;02H Use the ^ and v keys to select which entry is highlighted.
Press enter to boot the selected OS, `e' to edit the commands
before booting or `c' for a command-line. [05;80H
[05;03H luv [01D[0m[30m[47m[06;03H*sbbr/sbsa [0m[37m[40m[01D[07;03H [01D[08;03H [01D[09;03H [01D[10;03H [01D[11;03H [01D[12;03H [01D[13;03H [01D[14;03H [01D[15;03H [01D[16;03H [01D[17;03H [01D[02C
[06;78H[23;01H The highlighted entry will be executed automatically in 10s. [06;78H[23;01H The highlighted entry will be executed automatically in 9s. [06;78H[23;01H The highlighted entry will be executed automatically in 8s. [06;78H[23;01H The highlighted entry will be executed automatically in 7s. [06;78H[23;01H The highlighted entry will be executed automatically in 6s. [06;78H[23;01H The highlighted entry will be executed automatically in 5s. [06;78H[23;01H The highlighted entry will be executed automatically in 4s. [06;78H[23;01H The highlighted entry will be executed automatically in 3s. [06;78H[23;01H The highlighted entry will be executed automatically in 2s. [06;78H[23;01H The highlighted entry will be executed automatically in 1s. [06;78H[23;01H The highlighted entry will be executed automatically in 0s. [06;78H[0m[30m[40m[2J[01;01H[0m[37m[40m[0m[30m[40m[2J[04D[0m[37m[40m Booting `sbbr/sbsa'
/EndEntire
file path: /HardwareVendor(0d51905b-b77e-452a-a2c0-eca0cc8d514a)[9: 00 00 10 60
00 00 00 00 00 ]/Sata(0,ffff,0)/HD(2,40800,47000,026c6fdf3eb40948,2,2)
/File(\EFI\BOOT)/File(Shell.efi)/EndEntire
[2J[01;01HUEFI Interactive Shell v2.2
EDK II
UEFI v2.70 (EDK II, 0x00010000)
[1m[33m[40mMapping table[0m[37m[40m
[1m[33m[40m FS0:[0m[37m[40m [1m[37m[40mAlias(s):[0m[37m[40mHD0a65535a1:;BLK1:
VenHw(0D51905B-B77E-452A-A2C0-ECA0CC8D514A,000010600000000000)/Sata(0x
0,0xFFFF,0x0)/HD(1,GPT,DCC994A8-3772-4BF4-9936-D237B349809B,0x800,0x40000)
[1m[33m[40m FS1:[0m[37m[40m [1m[37m[40mAlias(s):[0m[37m[40mHD0a65535a2:;BLK2:
VenHw(0D51905B-B77E-452A-A2C0-ECA0CC8D514A,000010600000000000)/Sata(0x
0,0xFFFF,0x0)/HD(2,GPT,DF6F6C02-B43E-4809-8DB0-36633A94248A,0x40800,0x47000)
[1m[33m[40m BLK3:[0m[37m[40m [1m[37m[40mAlias(s):[0m[37m[40m
VenHw(93E34C7E-B50E-11DF-9223-2443DFD72085,00)
[1m[33m[40m BLK0:[0m[37m[40m [1m[37m[40mAlias(s):[0m[37m[40m
VenHw(0D51905B-B77E-452A-A2C0-ECA0CC8D514A,000010600000000000)/Sata(0x
0,0xFFFF,0x0)
Press [1m[37m[40mESC[0m[37m[40m in 5 seconds to skip [1m[33m[40mstartup.nsh[0m[37m[40m or any other key to continue.[72DPress [1m[37m[40mESC[0m[37m[40m in 4 seconds to skip [1m[33m[40mstartup.nsh[0m[37m[40m or any other key to continue.[72DPress [1m[37m[40mESC[0m[37m[40m in 3 seconds to skip [1m[33m[40mstartup.nsh[0m[37m[40m or any other key to continue.[72DPress [1m[37m[40mESC[0m[37m[40m in 2 seconds to skip [1m[33m[40mstartup.nsh[0m[37m[40m or any other key to continue.[72DPress [1m[37m[40mESC[0m[37m[40m in 1 seconds to skip [1m[33m[40mstartup.nsh[0m[37m[40m or any other key to continue.
[1m[33m[40mShell> [0m[37m[40mecho -off
Press any key to stop the EFI SCT running
Press any key within 10 seconds Press any key within 9 seconds Press any key within 8 seconds Press any key within 7 seconds Press any key within 6 seconds Press any key within 5 seconds Press any key within 4 seconds Press any key within 3 seconds Press any key within 2 seconds Press any key within 1 seconds Installing SCT to Luv-results partition...
- [ok]
- [ok]
Running SCT Tests...
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qemu-system-aarch64: terminating on signal 15 from pid 28138 (timeout)
Build step 'Execute shell' marked build as failure
Hi All,
While making the MPIDR related changes in UEFI, i.e reading it
from QEMU's device tree based on Leif's patch I thought of
updating the SSDT and PPTT topologies to match it.
The current SSDT table is implemented without a cluster and core
kind of topology. So it looks as follows
Scope (_SB) {
Device (C000) {
Name (_HID, "ACPI0007"),
Name (_UID, 0)
}
...
...
Device (Cxxx) {
Name (_HID, "ACPI0007"),
Name (_UID, coreid)
}
}
After looking at Graeme's TF-A tree, the topology would be as follows
- No SMT since MT bit isn't set
- Cluster with upto 8 Cores
- N clusters which is set at 64 currently
So I'm thinking to updating SSDT table with the following structure
Scope (_SB) {
Device (CL00) { // Cluster 0
Name (_HID, "ACPI0010"),
Name (_UID, 0x0)
Device (CP00) { // Cluster 0 Cpu0
Name (_HID, "ACPI0007"),
Name (_UID, (clusterid | 0x0)),
}
...
Device (CP07) { // Cluster 0 Cpu 7
Name (_HID, "ACPI0007"),
Name (_UID, (clusterid | coreid)),
}
}
...
...
Device (CLXX) { // Cluster 63
Name (_HID, "ACPI0010"),
Name (_UID, clusteridx)
Device (CP00) { // Cluster 63 Cpu 0
Name (_HID, "ACPI0007"),
Name (_UID, (clusteridx | coreidx)),
}
...
Device (CP07) { // Cluster 63 CPU 7
Name (_HID, "ACPI0007"),
Name (_UID, (clusteridx | coreidx)),
}
}
}
Can you please review this structure and let me know if I can
go ahead and make these changes in SSDT and PPTT table generation ?
With Regards,
Tanmay
Hi Leif,
Thank you very much for your feedback.
On Wed, 12 Aug 2020 at 19:41, Leif Lindholm via Asa-dev
<asa-dev(a)op-lists.linaro.org> wrote:
>
> Hi all,
>
> We've started looking at the TF-A qemu_sbsa port a bit, and found some
> things that were carried over from the mach-virt port for no good
> reason:
>
> Looking at plat/qemu/qemu_sbsa/platform.mk:
> - lib/cpus/aarch64/aem_generic.S is for fast models/foundation model.
> - although we may want to add a "generic armv8 cpu" to TF-A at some
> point, to reduce synchronization needs when bumping the cpu
> used by sbsa-ref in upstream QEMU.
For now, do we need to remove lib/cpus/aarch64/aem_generic.S
and lib/cpus/aarch64/cortex_a57.S from sbsa-qemu?
> - lib/cpus/aarch64/cortex_a53.S is not supported by sbsa-ref, nor does
> the A53 support enough physical address bits to be able to control
> this platform.
I'm not familiar with this item, is this a matter of QEMU side?
> - drivers/io/io_semihosting.c, lib/semihosting/semihosting.c, and
> lib/semihosting/${ARCH}/semihosting_call.S are not actually used.
> But there *are* some other bits of qemu/common code which needs to
> be cinditionalized-out if these files aren't included.
We are not using semi-hosting, I will try to remove these files
from the build target.
> - plat/common/plat_psci_common.c
> - all of the ${ARCH} stanzas should just be 'aarch64', this platform
> cannot be booted in aarch32.
I will fix this.
> - plat/common/plat_psci_common.c isn't usefully hooked up to anything
> at the moment, but we can fix that when we get to actually
> implementing useful PSCI. That file may simply not belong in
> 'common'.
I'm still checking the contents of plat/common/plat_psci_common.c, most of the
functions are optional.
Regards,
Masahisa
>
> /
> Leif
>
> --
> Asa-dev mailing list
> Asa-dev(a)op-lists.linaro.org
> https://op-lists.linaro.org/mailman/listinfo/asa-dev
On Tue, Aug 25, 2020 at 12:34:20PM +0000, Masahisa Kojima via Asa-dev wrote:
> Hi Leif,
>
> Thank you very much for your feedback.
>
> On Wed, 12 Aug 2020 at 19:41, Leif Lindholm via Asa-dev
> <asa-dev(a)op-lists.linaro.org> wrote:
> >
> > Hi all,
> >
> > We've started looking at the TF-A qemu_sbsa port a bit, and found some
> > things that were carried over from the mach-virt port for no good
> > reason:
> >
> > Looking at plat/qemu/qemu_sbsa/platform.mk:
> > - lib/cpus/aarch64/aem_generic.S is for fast models/foundation model.
> > - although we may want to add a "generic armv8 cpu" to TF-A at some
> > point, to reduce synchronization needs when bumping the cpu
> > used by sbsa-ref in upstream QEMU.
>
> For now, do we need to remove lib/cpus/aarch64/aem_generic.S
> and lib/cpus/aarch64/cortex_a57.S from sbsa-qemu?
>
> > - lib/cpus/aarch64/cortex_a53.S is not supported by sbsa-ref, nor does
> > the A53 support enough physical address bits to be able to control
> > this platform.
>
> I'm not familiar with this item, is this a matter of QEMU side?
>
> > - drivers/io/io_semihosting.c, lib/semihosting/semihosting.c, and
> > lib/semihosting/${ARCH}/semihosting_call.S are not actually used.
> > But there *are* some other bits of qemu/common code which needs to
> > be cinditionalized-out if these files aren't included.
>
> We are not using semi-hosting, I will try to remove these files
> from the build target.
>
> > - plat/common/plat_psci_common.c
> > - all of the ${ARCH} stanzas should just be 'aarch64', this platform
> > cannot be booted in aarch32.
>
> I will fix this.
>
> > - plat/common/plat_psci_common.c isn't usefully hooked up to anything
> > at the moment, but we can fix that when we get to actually
> > implementing useful PSCI. That file may simply not belong in
> > 'common'.
>
> I'm still checking the contents of plat/common/plat_psci_common.c, most of the
> functions are optional.
>
Hi Masahisa, thanks for taking this on, just for your information I have
been working on PSCI communicating with QEMU for shutdown/reset purposes
so have currently this branch of stuff I had to break out of common qemu
directory.
https://github.com/xXorAa/trusted-firmware-a/tree/secure-ec-wip
But I haven't done an in depth cleanup yet to make it more fine grained
so if you have any comments or advice based on your work they would be
greatfully received.
Thanks
Graeme
On Fri, 21 Aug 2020, at 11:34 AM, Masahisa Kojima via Asa-dev wrote:
> Hi all,
>
> I make StandaloneMM with secure varstore work on SBSA-QEMU.
>
> One item I would like to discuss is the location of non-secure shared memory
> between UEFI and Secure-EL0(StandaloneMM).
>
> For StandaloneMM, non-secure shared memory must be defined
> in compile time, because there is no method to know the
> shared memory address between uefi and tf-a in runtime.
>
I maybe missing something here, but ARM-TF can and does pass on a DT to edk2, can this not be defined there?
Graeme
> I allocated this non-secure shared memory at the bottom of the DRAM,
> because DRAM size varies depending on the QEMU parameter.
>
> DRAM layout is as follows(when the DRAM size is 1GB)
> 0x10000000000 - 0x10000FFFFFF(16MB) non-secure shared memory for StandaloneMM
> 0x10001000000 - 0x1003FFFFFFF(1GB - 16MB)
>
> Does anyone have comments on this?
> My concern is allocating something at the bottom of the DRAM is not
> the usual implementation?
> # Other packages like SGI allocate it at the top of DRAM.
>
> https://github.com/tianocore/edk2-platforms/blob/master/Platform/ARM/SgiPkg…
>
> --- patch ---
> diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
> b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
> index 7d9a9cc50bf3..7ec5669615f0 100644
> --- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
> +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
> @@ -387,7 +387,8 @@ [PcdsFixedAtBuild.common]
> gArmTokenSpaceGuid.PcdVFPEnabled|1
>
> # System Memory Base -- fixed
> - gArmTokenSpaceGuid.PcdSystemMemoryBase|0x10000000000
> + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x10001000000
>
> diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuMem.c
> b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuMem.c
> index 8c2eb0b6a028..7af9f5a4a1dc 100644
> --- a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuMem.c
> +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuMem.c
> @@ -73,8 +73,13 @@ SbsaQemuLibConstructor (
> }
> }
>
> + // For StandaloneMM Non-Secure Shared buffer, reserve 16MB
> + // at the bottom of DRAM.
> + NewSize -= 0x1000000;
> +
> // Make sure the start of DRAM matches our expectation
> - ASSERT (FixedPcdGet64 (PcdSystemMemoryBase) == NewBase);
> + // remove base address check
> +// ASSERT (FixedPcdGet64 (PcdSystemMemoryBase) == NewBase);
> PcdStatus = PcdSet64S (PcdSystemMemorySize, NewSize);
> ------
>
> Regards,
> Masahisa
> --
> Asa-dev mailing list
> Asa-dev(a)op-lists.linaro.org
> https://op-lists.linaro.org/mailman/listinfo/asa-dev
>
Hi all,
I make StandaloneMM with secure varstore work on SBSA-QEMU.
One item I would like to discuss is the location of non-secure shared memory
between UEFI and Secure-EL0(StandaloneMM).
For StandaloneMM, non-secure shared memory must be defined
in compile time, because there is no method to know the
shared memory address between uefi and tf-a in runtime.
I allocated this non-secure shared memory at the bottom of the DRAM,
because DRAM size varies depending on the QEMU parameter.
DRAM layout is as follows(when the DRAM size is 1GB)
0x10000000000 - 0x10000FFFFFF(16MB) non-secure shared memory for StandaloneMM
0x10001000000 - 0x1003FFFFFFF(1GB - 16MB)
Does anyone have comments on this?
My concern is allocating something at the bottom of the DRAM is not
the usual implementation?
# Other packages like SGI allocate it at the top of DRAM.
https://github.com/tianocore/edk2-platforms/blob/master/Platform/ARM/SgiPkg…
--- patch ---
diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
index 7d9a9cc50bf3..7ec5669615f0 100644
--- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
+++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
@@ -387,7 +387,8 @@ [PcdsFixedAtBuild.common]
gArmTokenSpaceGuid.PcdVFPEnabled|1
# System Memory Base -- fixed
- gArmTokenSpaceGuid.PcdSystemMemoryBase|0x10000000000
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x10001000000
diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuMem.c
b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuMem.c
index 8c2eb0b6a028..7af9f5a4a1dc 100644
--- a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuMem.c
+++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuMem.c
@@ -73,8 +73,13 @@ SbsaQemuLibConstructor (
}
}
+ // For StandaloneMM Non-Secure Shared buffer, reserve 16MB
+ // at the bottom of DRAM.
+ NewSize -= 0x1000000;
+
// Make sure the start of DRAM matches our expectation
- ASSERT (FixedPcdGet64 (PcdSystemMemoryBase) == NewBase);
+ // remove base address check
+// ASSERT (FixedPcdGet64 (PcdSystemMemoryBase) == NewBase);
PcdStatus = PcdSet64S (PcdSystemMemorySize, NewSize);
------
Regards,
Masahisa