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[RFC PATCH 1/2] hw/arm/sbsa-ref: Enable CXL Host Bridge by pxb-cxl

by Yuquan Wang

The memory layout places 1M space for 16 host bridge register regions in the sbsa-ref memmap. In addition, this creates a default pxb-cxl (bus_nr=0xfe) bridge with one cxl-rp on sbsa-ref. Signed-off-by: Yuquan Wang <wangyuquan1236(a)phytium.com.cn> --- hw/arm/sbsa-ref.c | 54 ++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 51 insertions(+), 3 deletions(-) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index ae37a92301..dc924d181e 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -41,7 +41,10 @@ #include "hw/intc/arm_gicv3_common.h" #include "hw/intc/arm_gicv3_its_common.h" #include "hw/loader.h" +#include "hw/pci/pci_bridge.h" +#include "hw/pci/pci_bus.h" #include "hw/pci-host/gpex.h" +#include "hw/pci-bridge/pci_expander_bridge.h" #include "hw/qdev-properties.h" #include "hw/usb.h" #include "hw/usb/xhci.h" @@ -52,6 +55,8 @@ #include "qom/object.h" #include "target/arm/cpu-qom.h" #include "target/arm/gtimer.h" +#include "hw/cxl/cxl.h" +#include "hw/cxl/cxl_host.h" #define RAMLIMIT_GB 8192 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) @@ -94,6 +99,7 @@ enum { SBSA_SECURE_MEM, SBSA_AHCI, SBSA_XHCI, + SBSA_CXL_HOST, }; struct SBSAMachineState { @@ -105,6 +111,9 @@ struct SBSAMachineState { int psci_conduit; DeviceState *gic; PFlashCFI01 *flash[2]; + CXLState cxl_devices_state; + PCIBus *bus; + PCIBus *cxlbus; }; #define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref") @@ -132,6 +141,8 @@ static const MemMapEntry sbsa_ref_memmap[] = { /* Space here reserved for more SMMUs */ [SBSA_AHCI] = { 0x60100000, 0x00010000 }, [SBSA_XHCI] = { 0x60110000, 0x00010000 }, + /* 1M CXL Host Bridge Registers space (64KiB * 16) */ + [SBSA_CXL_HOST] = { 0x60120000, 0x00100000 }, /* Space here reserved for other devices */ [SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 }, /* 32-bit address PCIE MMIO space */ @@ -631,6 +642,26 @@ static void create_smmu(const SBSAMachineState *sms, PCIBus *bus) } } +static void create_pxb_cxl(SBSAMachineState *sms) +{ + CXLHost *host; + PCIHostState *cxl; + + sms->cxl_devices_state.is_enabled = true; + + DeviceState *qdev; + qdev = qdev_new(TYPE_PXB_CXL_DEV); + qdev_prop_set_uint32(qdev, "bus_nr", 0xfe); + + PCIDevice *dev = PCI_DEVICE(qdev); + pci_realize_and_unref(dev, sms->bus, &error_fatal); + + host = PXB_CXL_DEV(dev)->cxl_host_bridge; + cxl = PCI_HOST_BRIDGE(host); + sms->cxlbus = cxl->bus; + pci_create_simple(sms->cxlbus, -1, "cxl-rp"); +} + static void create_pcie(SBSAMachineState *sms) { hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base; @@ -682,12 +713,25 @@ static void create_pcie(SBSAMachineState *sms) } pci = PCI_HOST_BRIDGE(dev); + sms->bus = pci->bus; + + pci_init_nic_devices(sms->bus, mc->default_nic); - pci_init_nic_devices(pci->bus, mc->default_nic); + pci_create_simple(sms->bus, -1, "bochs-display"); - pci_create_simple(pci->bus, -1, "bochs-display"); + create_smmu(sms, sms->bus); - create_smmu(sms, pci->bus); + create_pxb_cxl(sms); +} + +static void create_cxl_host_reg_region(SBSAMachineState *sms) +{ + MemoryRegion *sysmem = get_system_memory(); + MemoryRegion *mr = &sms->cxl_devices_state.host_mr; + + memory_region_init(mr, OBJECT(sms), "cxl_host_reg", + sbsa_ref_memmap[SBSA_CXL_HOST].size); + memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_CXL_HOST].base, mr); } static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size) @@ -823,6 +867,10 @@ static void sbsa_ref_init(MachineState *machine) create_pcie(sms); + create_cxl_host_reg_region(sms); + + cxl_hook_up_pxb_registers(sms->bus, &sms->cxl_devices_state, &error_fatal); + create_secure_ec(secure_sysmem); sms->bootinfo.ram_size = machine->ram_size; -- 2.34.1 信息安全声明：本邮件包含信息归发件人所在组织所有,发件人所在组织对该邮件拥有所有权利。请接收者注意保密,未经发件人书面许可,不得向任何第三方组织和个人透露本邮件所含信息。 Information Security Notice: The information contained in this mail is solely property of the sender's organization.This mail communication is confidential.Recipients named above are obligated to maintain secrecy and are not permitted to disclose the contents of this communication to others.

3 months, 3 weeks

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[RFC PATCH edk2-platforms 0/2] add basic support for CXL on sbsa-ref

by Yuquan Wang

RFC because - Many contents are ported from Jonathan' patch on qemu virt design - Bring plenty of PCDs values and modifying the original PCIE values - Less experience and not particularly confident in ACPI area so this might be stupidly broken in a way I've not considered. This series leverages Jonathan's patches[1] to add acpi0016 & acpi0017 objects into the previous DSDT table of sbsa-ref. Since the acpi0016 implementation model on qemu side is the pxb-cxl, this cxl Bus would share the MMIO space and ECAM sapce of PCIE Bus. Thus I divide some space from PciMmio32、PciMmio64、PciExpressBar to support cxl-related values. Based on the new CEDT definitions patch on edk2[2], this series adds a static Cedt.aslc to support the [SBSA_CXL_HOST] & [SBSA_CXL_FIXED_WINDOW] space on sbsa-ref. Since I was first developing this platform design for cxl, at the initial stage I only reserved one cxl host bridge (Bus: 0000:fe) and a cxl root port underneath (fe:00.0), therefore, only one cxl device(ff:00.0)could be added by user on this cxl Bus. Link: [1]: https://lore.kernel.org/linux-cxl/20220616141950.23374-2-Jonathan.Cameron@h… [2]: https://edk2.groups.io/g/devel/topic/rfc_patch_0_1/108173029 Yuquan Wang (2): SbsaQemu: Add acpi0016 & acpi0017 objects into DSDT SbsaQemu: AcpiTables: Add CEDT Table Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 30 +- .../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 20 +- Silicon/Qemu/SbsaQemu/AcpiTables/Cedt.aslc | 70 +++ Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 410 +++++++++++++++++- Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc | 2 +- .../SbsaQemuPciHostBridgeLib.c | 4 +- .../SbsaQemuPciHostBridgeLib.inf | 3 + Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 34 +- 8 files changed, 555 insertions(+), 18 deletions(-) create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Cedt.aslc -- 2.34.1 信息安全声明：本邮件包含信息归发件人所在组织所有,发件人所在组织对该邮件拥有所有权利。请接收者注意保密,未经发件人书面许可,不得向任何第三方组织和个人透露本邮件所含信息。 Information Security Notice: The information contained in this mail is solely property of the sender's organization.This mail communication is confidential.Recipients named above are obligated to maintain secrecy and are not permitted to disclose the contents of this communication to others. 信息安全声明：本邮件包含信息归发件人所在组织所有,发件人所在组织对该邮件拥有所有权利。请接收者注意保密,未经发件人书面许可,不得向任何第三方组织和个人透露本邮件所含信息。 Information Security Notice: The information contained in this mail is solely property of the sender's organization.This mail communication is confidential.Recipients named above are obligated to maintain secrecy and are not permitted to disclose the contents of this communication to others.

3 months, 3 weeks

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[RFC PATCH edk2-platforms 2/2] SbsaQemu: AcpiTables: Add CEDT Table

by Yuquan Wang

Provide CXL Early Discovery Table that describes the static CXL Platform Components of sbsa-ref. This adds a static CXL Host Bridge structure and a CXL Fixed Memory Window structure which are implemented as two independent space on sbsa-ref: [SBSA_CXL_HOST] & [SBSA_CXL_FIXED_WINDOW]. Signed-off-by: Yuquan Wang <wangyuquan1236(a)phytium.com.cn> --- .../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 6 +- Silicon/Qemu/SbsaQemu/AcpiTables/Cedt.aslc | 70 +++++++++++++++++++ Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 7 ++ 3 files changed, 82 insertions(+), 1 deletion(-) create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Cedt.aslc diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf index b4d5aa807bd9..f39b06d708d5 100644 --- a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf @@ -21,7 +21,7 @@ Fadt.aslc Mcfg.aslc Spcr.aslc - + Cedt.aslc [Packages] ArmPlatformPkg/ArmPlatformPkg.dec ArmPkg/ArmPkg.dec @@ -78,6 +78,10 @@ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlBarSize gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlBarLimit + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdChbcrBase + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCfmwsBase + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCfmwsSize + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformAhciBase diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Cedt.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Cedt.aslc new file mode 100644 index 000000000000..66c9dc8858bc --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Cedt.aslc @@ -0,0 +1,70 @@ +/** @file +* CXL Early Discovery Table (CEDT) +* +* Copyright (c) 2024, Phytium Technology Co Ltd. All rights reserved. +* +**/ + +#include <IndustryStandard/CXLEarlyDiscoveryTable.h> +#include <IndustryStandard/Acpi64.h> +#include <IndustryStandard/SbsaQemuAcpi.h> + +#pragma pack(1) + +typedef struct +{ + EFI_ACPI_6_4_CXL_Early_Discovery_TABLE Header; + EFI_ACPI_6_4_CXL_Host_Bridge_Structure Chbs; + EFI_ACPI_6_4_CXL_Fixed_Memory_Window_Structure Cfmws; +} SBSA_REF_CEDT; + + +SBSA_REF_CEDT Cedt = +{ + // EFI_ACPI_6_4_CXL_Early_Discovery_TABLE(Header) + { + SBSAQEMU_ACPI_HEADER // EFI_ACPI_DESCRIPTION_HEADER + ( + EFI_ACPI_6_4_CXL_EARLY_DISCOVERY_TABLE_SIGNATURE, + SBSA_REF_CEDT, + EFI_ACPI_CXL_Early_Discovery_TABLE_REVISION_01 + ), + }, + // EFI_ACPI_6_4_CXL_Host_Bridge_Structure + { + // EFI_ACPI_6_4_CEDT_Structure + { + EFI_ACPI_CEDT_TYPE_CHBS, // Type + 0, // Reserved + sizeof (EFI_ACPI_6_4_CXL_Host_Bridge_Structure), // Length + }, + FixedPcdGet32 (PcdCxlBusMin), // UID + 0x1, // CXLVersion + 0, // Reserved + FixedPcdGet32 (PcdChbcrBase), // CHBCR Base + 0X10000, // Length + }, + // EFI_ACPI_6_4_CXL_Fixed_Memory_Window_Structure + { + // EFI_ACPI_6_4_CEDT_Structure + { + EFI_ACPI_CEDT_TYPE_CFMWS, // Type + 0, // Reserved + sizeof (EFI_ACPI_6_4_CXL_Fixed_Memory_Window_Structure), // Length + }, + 0, // Reserved + FixedPcdGet32 (PcdCfmwsBase), // BaseHPA + FixedPcdGet32 (PcdCfmwsSize), // WindowSize + 0, // InterleaveMembers + 0, // InterleaveArithmetic + 0, // Reserved1 + 0, // Granularity + 0xF, // Restrictions + 0, // QtgId + FixedPcdGet32 (PcdCxlBusMin), // FirstTarget + } +}; + +#pragma pack () + +VOID* CONST ReferenceAcpiTable = &Cedt; diff --git a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec index 7d8c7997160b..dff838315d06 100644 --- a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec +++ b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec @@ -65,6 +65,13 @@ HardwareInfoLib|Include/Library/HardwareInfoLib.h gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlBusMin|254|UINT32|0x00000019 gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlBusMax|255|UINT32|0x00000020 + # PCDs complementing base address for CXL CHBCR (CXL Host Bridge Component Registers) + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdChbcrBase|0x60120000|UINT64|0x00000021 + + # CXL Fixed Memory Window + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCfmwsBase|0xA0000000000|UINT64|0x00000022 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCfmwsSize|0x10000000000|UINT64|0x00000023 + [PcdsDynamic.common] gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdSystemManufacturer|L""|VOID*|0x00000110 gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdSystemSerialNumber|L""|VOID*|0x00000111 -- 2.34.1 信息安全声明：本邮件包含信息归发件人所在组织所有,发件人所在组织对该邮件拥有所有权利。请接收者注意保密,未经发件人书面许可,不得向任何第三方组织和个人透露本邮件所含信息。 Information Security Notice: The information contained in this mail is solely property of the sender's organization.This mail communication is confidential.Recipients named above are obligated to maintain secrecy and are not permitted to disclose the contents of this communication to others.

3 months, 3 weeks

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[RFC PATCH edk2-platforms 1/2] SbsaQemu: Add acpi0016 & acpi0017 objects into DSDT

by Yuquan Wang

This adds relevant definitions and descriptions of acpi0016 and acpi0017 to support CXL. With the implementation of pxb-cxl on the original pcie host bridge, the previous space layout of mmio32 & mmio64 have to be divided to provide the mmio space for cxl host bridge. I'm not sure if the new space layout would bring a series of bad influence, but it seems that the base address and size of cxl host bridge is ok. Signed-off-by: Yuquan Wang <wangyuquan1236(a)phytium.com.cn> --- Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 30 +- .../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 14 + Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 410 +++++++++++++++++- Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc | 2 +- .../SbsaQemuPciHostBridgeLib.c | 4 +- .../SbsaQemuPciHostBridgeLib.inf | 3 + Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 27 +- 7 files changed, 473 insertions(+), 17 deletions(-) diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc index 9f54a8915707..5694c0bc8b01 100644 --- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc @@ -452,23 +452,39 @@ DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE # # ECAM size == 0x10000000 gArmTokenSpaceGuid.PcdPciBusMin|0 - gArmTokenSpaceGuid.PcdPciBusMax|255 + gArmTokenSpaceGuid.PcdPciBusMax|253 gArmTokenSpaceGuid.PcdPciIoBase|0x0 gArmTokenSpaceGuid.PcdPciIoSize|0x00010000 gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciIoLimit|0x0000ffff gArmTokenSpaceGuid.PcdPciMmio32Base|0x80000000 - gArmTokenSpaceGuid.PcdPciMmio32Size|0x70000000 - gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciMmio32Limit|0xEFFFFFFF + gArmTokenSpaceGuid.PcdPciMmio32Size|0x6FE00000 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciMmio32Limit|0xEFDFFFFF gArmTokenSpaceGuid.PcdPciMmio64Base|0x100000000 - gArmTokenSpaceGuid.PcdPciMmio64Size|0xFF00000000 - gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciMmio64Limit|0xFFFFFFFFFF + gArmTokenSpaceGuid.PcdPciMmio64Size|0xFEFFFF0000 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciMmio64Limit|0xFFFFFEFFFF + + # + # CXL Host Bridge (pxb-cxl on PCI Root Complex) + # + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlBusMin|254 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlBusMax|255 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlMmio32Base|0xEFE00000 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlMmio32Size|0x00200000 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlMmio64Base|0xFFFFFF0000 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlMmio64Size|0x000010000 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlMmio32Limit|0xEFFFFFFF + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlMmio64Limit|0xFFFFFFFFFF # set PcdPciExpressBaseAddress to MAX_UINT64, which signifies that this # PCD and PcdPciDisableBusEnumeration have not been assigned yet # TODO: PcdPciExpressBaseAddress set to max_uint64 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xf0000000 - gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarSize|0x10000000 - gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarLimit|0xFFFFFFFF + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarSize|0x0FE00000 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarLimit|0xFFDFFFFF + # PCDs complementing CXL ECAM Base & Size + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlBaseAddress|0xFFE00000 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlBarSize|0x00200000 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlBarLimit|0xFFFFFFFF gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation|0x7fff0000 gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation|0x0 diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf index 8d4905362edc..b4d5aa807bd9 100644 --- a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf @@ -44,6 +44,8 @@ gArmTokenSpaceGuid.PcdPciBusMin gArmTokenSpaceGuid.PcdPciBusMax + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlBusMin + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlBusMax gArmTokenSpaceGuid.PcdPciIoBase gArmTokenSpaceGuid.PcdPciIoSize @@ -60,10 +62,22 @@ gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciMmio64Limit + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlMmio32Base + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlMmio32Size + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlMmio32Limit + + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlMmio64Base + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlMmio64Size + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlMmio64Limit + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarSize gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarLimit + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlBaseAddress + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlBarSize + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlBarLimit + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformAhciBase diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl index c134fb66e860..94d0b2cbb118 100644 --- a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl @@ -182,6 +182,372 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", } // USB0_RHUB } // USB0 + // CXL Host Bridge (pxb-cxl) + Device (PC0C) + { + Name (_HID, "ACPI0016" /* Compute Express Link Host Bridge */) // _HID: Hardware ID + Name (_CID, Package (0x02) // _CID: Compatible ID + { + EisaId ("PNP0A08"), /* PCI Express Bus */ + EisaId ("PNP0A03") /* PCI Bus */ + }) + Name (_BBN, 0xFE) // _BBN: BIOS Bus Number + Name (_UID, 0xFE) // _UID: Unique ID + Name (_STR, Unicode ("pxb Device")) // _STR: Description String + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_PRT, Package (0x80) // _PRT: PCI Routing Table + { + PRT_ENTRY(0x0000FFFF, 0, GSI0), + PRT_ENTRY(0x0000FFFF, 1, GSI1), + PRT_ENTRY(0x0000FFFF, 2, GSI2), + PRT_ENTRY(0x0000FFFF, 3, GSI3), + + PRT_ENTRY(0x0001FFFF, 0, GSI1), + PRT_ENTRY(0x0001FFFF, 1, GSI2), + PRT_ENTRY(0x0001FFFF, 2, GSI3), + PRT_ENTRY(0x0001FFFF, 3, GSI0), + + PRT_ENTRY(0x0002FFFF, 0, GSI2), + PRT_ENTRY(0x0002FFFF, 1, GSI3), + PRT_ENTRY(0x0002FFFF, 2, GSI0), + PRT_ENTRY(0x0002FFFF, 3, GSI1), + + PRT_ENTRY(0x0003FFFF, 0, GSI3), + PRT_ENTRY(0x0003FFFF, 1, GSI0), + PRT_ENTRY(0x0003FFFF, 2, GSI1), + PRT_ENTRY(0x0003FFFF, 3, GSI2), + + PRT_ENTRY(0x0004FFFF, 0, GSI0), + PRT_ENTRY(0x0004FFFF, 1, GSI1), + PRT_ENTRY(0x0004FFFF, 2, GSI2), + PRT_ENTRY(0x0004FFFF, 3, GSI3), + + PRT_ENTRY(0x0005FFFF, 0, GSI1), + PRT_ENTRY(0x0005FFFF, 1, GSI2), + PRT_ENTRY(0x0005FFFF, 2, GSI3), + PRT_ENTRY(0x0005FFFF, 3, GSI0), + + PRT_ENTRY(0x0006FFFF, 0, GSI2), + PRT_ENTRY(0x0006FFFF, 1, GSI3), + PRT_ENTRY(0x0006FFFF, 2, GSI0), + PRT_ENTRY(0x0006FFFF, 3, GSI1), + + PRT_ENTRY(0x0007FFFF, 0, GSI3), + PRT_ENTRY(0x0007FFFF, 1, GSI0), + PRT_ENTRY(0x0007FFFF, 2, GSI1), + PRT_ENTRY(0x0007FFFF, 3, GSI2), + + PRT_ENTRY(0x0008FFFF, 0, GSI0), + PRT_ENTRY(0x0008FFFF, 1, GSI1), + PRT_ENTRY(0x0008FFFF, 2, GSI2), + PRT_ENTRY(0x0008FFFF, 3, GSI3), + + PRT_ENTRY(0x0009FFFF, 0, GSI1), + PRT_ENTRY(0x0009FFFF, 1, GSI2), + PRT_ENTRY(0x0009FFFF, 2, GSI3), + PRT_ENTRY(0x0009FFFF, 3, GSI0), + + PRT_ENTRY(0x000AFFFF, 0, GSI2), + PRT_ENTRY(0x000AFFFF, 1, GSI3), + PRT_ENTRY(0x000AFFFF, 2, GSI0), + PRT_ENTRY(0x000AFFFF, 3, GSI1), + + PRT_ENTRY(0x000BFFFF, 0, GSI3), + PRT_ENTRY(0x000BFFFF, 1, GSI0), + PRT_ENTRY(0x000BFFFF, 2, GSI1), + PRT_ENTRY(0x000BFFFF, 3, GSI2), + + PRT_ENTRY(0x000CFFFF, 0, GSI0), + PRT_ENTRY(0x000CFFFF, 1, GSI1), + PRT_ENTRY(0x000CFFFF, 2, GSI2), + PRT_ENTRY(0x000CFFFF, 3, GSI3), + + PRT_ENTRY(0x000DFFFF, 0, GSI1), + PRT_ENTRY(0x000DFFFF, 1, GSI2), + PRT_ENTRY(0x000DFFFF, 2, GSI3), + PRT_ENTRY(0x000DFFFF, 3, GSI0), + + PRT_ENTRY(0x000EFFFF, 0, GSI2), + PRT_ENTRY(0x000EFFFF, 1, GSI3), + PRT_ENTRY(0x000EFFFF, 2, GSI0), + PRT_ENTRY(0x000EFFFF, 3, GSI1), + + PRT_ENTRY(0x000FFFFF, 0, GSI3), + PRT_ENTRY(0x000FFFFF, 1, GSI0), + PRT_ENTRY(0x000FFFFF, 2, GSI1), + PRT_ENTRY(0x000FFFFF, 3, GSI2), + + PRT_ENTRY(0x0010FFFF, 0, GSI0), + PRT_ENTRY(0x0010FFFF, 1, GSI1), + PRT_ENTRY(0x0010FFFF, 2, GSI2), + PRT_ENTRY(0x0010FFFF, 3, GSI3), + + PRT_ENTRY(0x0011FFFF, 0, GSI1), + PRT_ENTRY(0x0011FFFF, 1, GSI2), + PRT_ENTRY(0x0011FFFF, 2, GSI3), + PRT_ENTRY(0x0011FFFF, 3, GSI0), + + PRT_ENTRY(0x0012FFFF, 0, GSI2), + PRT_ENTRY(0x0012FFFF, 1, GSI3), + PRT_ENTRY(0x0012FFFF, 2, GSI0), + PRT_ENTRY(0x0012FFFF, 3, GSI1), + + PRT_ENTRY(0x0013FFFF, 0, GSI3), + PRT_ENTRY(0x0013FFFF, 1, GSI0), + PRT_ENTRY(0x0013FFFF, 2, GSI1), + PRT_ENTRY(0x0013FFFF, 3, GSI2), + + PRT_ENTRY(0x0014FFFF, 0, GSI0), + PRT_ENTRY(0x0014FFFF, 1, GSI1), + PRT_ENTRY(0x0014FFFF, 2, GSI2), + PRT_ENTRY(0x0014FFFF, 3, GSI3), + + PRT_ENTRY(0x0015FFFF, 0, GSI1), + PRT_ENTRY(0x0015FFFF, 1, GSI2), + PRT_ENTRY(0x0015FFFF, 2, GSI3), + PRT_ENTRY(0x0015FFFF, 3, GSI0), + + PRT_ENTRY(0x0016FFFF, 0, GSI2), + PRT_ENTRY(0x0016FFFF, 1, GSI3), + PRT_ENTRY(0x0016FFFF, 2, GSI0), + PRT_ENTRY(0x0016FFFF, 3, GSI1), + + PRT_ENTRY(0x0017FFFF, 0, GSI3), + PRT_ENTRY(0x0017FFFF, 1, GSI0), + PRT_ENTRY(0x0017FFFF, 2, GSI1), + PRT_ENTRY(0x0017FFFF, 3, GSI2), + + PRT_ENTRY(0x0018FFFF, 0, GSI0), + PRT_ENTRY(0x0018FFFF, 1, GSI1), + PRT_ENTRY(0x0018FFFF, 2, GSI2), + PRT_ENTRY(0x0018FFFF, 3, GSI3), + + PRT_ENTRY(0x0019FFFF, 0, GSI1), + PRT_ENTRY(0x0019FFFF, 1, GSI2), + PRT_ENTRY(0x0019FFFF, 2, GSI3), + PRT_ENTRY(0x0019FFFF, 3, GSI0), + + PRT_ENTRY(0x001AFFFF, 0, GSI2), + PRT_ENTRY(0x001AFFFF, 1, GSI3), + PRT_ENTRY(0x001AFFFF, 2, GSI0), + PRT_ENTRY(0x001AFFFF, 3, GSI1), + + PRT_ENTRY(0x001BFFFF, 0, GSI3), + PRT_ENTRY(0x001BFFFF, 1, GSI0), + PRT_ENTRY(0x001BFFFF, 2, GSI1), + PRT_ENTRY(0x001BFFFF, 3, GSI2), + + PRT_ENTRY(0x001CFFFF, 0, GSI0), + PRT_ENTRY(0x001CFFFF, 1, GSI1), + PRT_ENTRY(0x001CFFFF, 2, GSI2), + PRT_ENTRY(0x001CFFFF, 3, GSI3), + + PRT_ENTRY(0x001DFFFF, 0, GSI1), + PRT_ENTRY(0x001DFFFF, 1, GSI2), + PRT_ENTRY(0x001DFFFF, 2, GSI3), + PRT_ENTRY(0x001DFFFF, 3, GSI0), + + PRT_ENTRY(0x001EFFFF, 0, GSI2), + PRT_ENTRY(0x001EFFFF, 1, GSI3), + PRT_ENTRY(0x001EFFFF, 2, GSI0), + PRT_ENTRY(0x001EFFFF, 3, GSI1), + + PRT_ENTRY(0x001FFFFF, 0, GSI3), + PRT_ENTRY(0x001FFFFF, 1, GSI0), + PRT_ENTRY(0x001FFFFF, 2, GSI1), + PRT_ENTRY(0x001FFFFF, 3, GSI2), + }) + Device (GSI0) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000023, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000023, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSI1) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000024, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000024, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSI2) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000025, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000025, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSI3) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000026, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000026, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + DWordMemory ( // 32-bit BAR Windows + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, // Granularity + FixedPcdGet32 (PcdCxlMmio32Base), // Min Base Address + FixedPcdGet32 (PcdCxlMmio32Limit), // Max Base Address + FixedPcdGet32 (PcdPciMmio32Translation), // Translate + FixedPcdGet32 (PcdCxlMmio32Size) // Length + ) + + QWordMemory ( // 64-bit BAR Windows + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, // Granularity + FixedPcdGet64 (PcdCxlMmio64Base), // Min Base Address + FixedPcdGet64 (PcdCxlMmio64Limit), // Max Base Address + FixedPcdGet64 (PcdPciMmio64Translation), // Translate + FixedPcdGet64 (PcdCxlMmio64Size) // Length + ) + + WordBusNumber ( // Bus numbers assigned to this root + ResourceProducer, + MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + FixedPcdGet32 (PcdCxlBusMin), // AddressMinimum - Minimum Bus Number + FixedPcdGet32 (PcdCxlBusMax), // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 2 // RangeLength - Number of Busses + ) + }) + + Device (RES0) + { + Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + FixedPcdGet64 (PcdCxlBaseAddress), // Range Minimum + FixedPcdGet64 (PcdCxlBarLimit), // Range Maximum + 0x0000000000000000, // Translation Offset + FixedPcdGet64 (PcdCxlBarSize), // Length + ,, , AddressRangeMemory, TypeStatic) + }) + Method (_STA) { + Return (0xF) + } + } + + Name (SUPP, Zero) + Name (CTRL, Zero) + Name (SUPC, Zero) + Name (CTRC, Zero) + + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, Zero, CDW1) + If (((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */) || (Arg0 == ToUUID ("68f2d50b-c469-4d8a-bd3d-941a103fd3fc") /* Unknown UUID */))) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + Local0 = CDW3 /* \_SB_.PC0C._OSC.CDW3 */ + Local0 &= 0x1F + If ((Arg1 != One)) + { + CDW1 |= 0x08 + } + + If ((CDW3 != Local0)) + { + CDW1 |= 0x10 + } + + SUPP = CDW2 /* \_SB_.PC0C._OSC.CDW2 */ + CTRL = CDW3 /* \_SB_.PC0C._OSC.CDW3 */ + CDW3 = Local0 + If ((Arg0 == ToUUID ("68f2d50b-c469-4d8a-bd3d-941a103fd3fc") /* Unknown UUID */)) + { + CreateDWordField (Arg3, 0x0C, CDW4) + CreateDWordField (Arg3, 0x10, CDW5) + SUPC = CDW4 /* \_SB_.PC0C._OSC.CDW4 */ + CTRC = CDW5 /* \_SB_.PC0C._OSC.CDW5 */ + CDW5 |= One + } + + Return (Arg3) + } + Else + { + CDW1 |= 0x04 + Return (Arg3) + } + } + } + Device (PCI0) { Name (_HID, EISAID ("PNP0A08")) // PCI Express Root Bridge @@ -376,7 +742,7 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", FixedPcdGet32 (PcdPciBusMin), // AddressMinimum - Minimum Bus Number FixedPcdGet32 (PcdPciBusMax), // AddressMaximum - Maximum Bus Number 0, // AddressTranslation - Set to 0 - 256 // RangeLength - Number of Busses + 254 // RangeLength - Number of Busses ) DWordMemory ( // 32-bit BAR Windows @@ -416,7 +782,7 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", ) }) // Name(_CRS) - Device (RES0) + Device (RES1) { Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings @@ -483,5 +849,45 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", } } // End _OSC } + + Scope (\_SB) + { + // CXL Root for OS Driver + Device (CXLM) + { + Name (_HID, "ACPI0017") // _HID: Hardware ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0B) + } + + Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method + { + If ((Arg0 == ToUUID ("f365f9a6-a7de-4071-a66a-b40c0b4f8e52") /* Unknown UUID */)) + { + If ((Arg2 == Zero)) + { + Return (Buffer (One) + { + 0x01 // . + }) + } + + If ((Arg2 == One)) + { + Return (Package (0x02) + { + One, + Package (0x02) + { + Zero, + One + } + }) + } + } + } + } + } } // Scope (_SB) } diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc index 289f4ad4ea3a..4fc03558b2b3 100644 --- a/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc @@ -30,7 +30,7 @@ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE Mcfg = { FixedPcdGet32 (PcdPciExpressBaseAddress), 0, FixedPcdGet32 (PcdPciBusMin), - FixedPcdGet32 (PcdPciBusMax), + FixedPcdGet32 (PcdCxlBusMax), EFI_ACPI_RESERVED_DWORD } } diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.c b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.c index 8994a5226289..33808fa1f388 100644 --- a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.c +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.c @@ -99,7 +99,7 @@ STATIC PCI_ROOT_BRIDGE mRootBridge = { (gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation as 0x0) */ { FixedPcdGet32 (PcdPciMmio32Base), - FixedPcdGet32 (PcdPciMmio32Base) + FixedPcdGet32 (PcdPciMmio32Size) - 1, + FixedPcdGet32 (PcdCxlMmio32Limit), }, /* PCI_ROOT_BRIDGE_APERTURE MemAbove4G; MMIO aperture above 4GB which can be @@ -107,7 +107,7 @@ STATIC PCI_ROOT_BRIDGE mRootBridge = { (gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation as 0x0) */ { FixedPcdGet64 (PcdPciMmio64Base), - FixedPcdGet64 (PcdPciMmio64Base) + FixedPcdGet64 (PcdPciMmio64Size) - 1 + FixedPcdGet64 (PcdCxlMmio64Limit) }, /* PCI_ROOT_BRIDGE_APERTURE PMem; Prefetchable MMIO aperture below 4GB which diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.inf b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.inf index 9d6791ff7dc2..7e7e36fd87bd 100644 --- a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.inf +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.inf @@ -29,6 +29,7 @@ ArmPkg/ArmPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec + Silicon/Qemu/SbsaQemu/SbsaQemu.dec [LibraryClasses] DebugLib @@ -42,6 +43,8 @@ gArmTokenSpaceGuid.PcdPciMmio32Size gArmTokenSpaceGuid.PcdPciMmio64Base gArmTokenSpaceGuid.PcdPciMmio64Size + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlMmio32Limit + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlMmio64Limit [Depex] TRUE diff --git a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec index 60daeff915c5..7d8c7997160b 100644 --- a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec +++ b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec @@ -39,14 +39,31 @@ HardwareInfoLib|Include/Library/HardwareInfoLib.h # PCDs complementing PCIe layout pulled into ACPI tables # Limit = Base + Size - 1 - gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciIoLimit|0x0000ffff|UINT32|0x00000006 - gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciMmio32Limit|0xEFFFFFFF|UINT32|0x00000007 - gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciMmio64Limit|0xFFFFFFFFFF|UINT64|0x00000008 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciIoLimit|0x0000ffff|UINT32|0x00000005 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciMmio32Limit|0xEFDFFFFF|UINT32|0x00000006 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciMmio64Limit|0xFFFFFEFFFF|UINT64|0x00000007 # PCDs complementing gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress # BarLimit = BaseAddress + BarSize - 1 - gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarSize|0x10000000|UINT64|0x00000009 - gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarLimit|0xFFFFFFFF|UINT64|0x00000010 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarSize|0x0FE00000|UINT64|0x00000008 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarLimit|0xFFDFFFFF|UINT64|0x00000009 + + # PCDs complementing CXL layout pulled into ACPI tables + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlMmio32Base|0xEFE00000|UINT32|0x00000010 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlMmio32Size|0x00200000|UINT32|0x00000011 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlMmio64Base|0xFFFFFF0000|UINT64|0x00000012 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlMmio64Size|0x000010000|UINT32|0x00000013 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlMmio32Limit|0xEFFFFFFF|UINT32|0x00000014 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlMmio64Limit|0xFFFFFFFFFF|UINT64|0x00000015 + + # PCDs complementing CXL ECAM Base & Size + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlBaseAddress|0xFFE00000|UINT64|0x00000016 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlBarSize|0x00200000|UINT64|0x00000017 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlBarLimit|0xFFFFFFFF|UINT64|0x00000018 + + # PCDs complementing CXL Bus Range + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlBusMin|254|UINT32|0x00000019 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlBusMax|255|UINT32|0x00000020 [PcdsDynamic.common] gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdSystemManufacturer|L""|VOID*|0x00000110 -- 2.34.1 信息安全声明：本邮件包含信息归发件人所在组织所有,发件人所在组织对该邮件拥有所有权利。请接收者注意保密,未经发件人书面许可,不得向任何第三方组织和个人透露本邮件所含信息。 Information Security Notice: The information contained in this mail is solely property of the sender's organization.This mail communication is confidential.Recipients named above are obligated to maintain secrecy and are not permitted to disclose the contents of this communication to others.

3 months, 3 weeks

1
0
0 0

[RFC PATCH edk2-platforms 0/2] add basic support for CXL on sbsa-ref

by Yuquan Wang

RFC because - Many contents are ported from Jonathan' patch on qemu virt design - Bring plenty of PCDs values and modifying the original PCIE values - Less experience and not particularly confident in ACPI area so this might be stupidly broken in a way I've not considered. This series leverages Jonathan's patches[1] to add acpi0016 & acpi0017 objects into the previous DSDT table of sbsa-ref. Since the acpi0016 implementation model on qemu side is the pxb-cxl, this cxl Bus would share the MMIO space and ECAM sapce of PCIE Bus. Thus I divide some space from PciMmio32、PciMmio64、PciExpressBar to support cxl-related values. Based on the new CEDT definitions patch on edk2[2], this series adds a static Cedt.aslc to support the [SBSA_CXL_HOST] & [SBSA_CXL_FIXED_WINDOW] space on sbsa-ref. Since I was first developing this platform design for cxl, at the initial stage I only reserved one cxl host bridge (Bus: 0000:fe) and a cxl root port underneath (fe:00.0), therefore, only one cxl device(ff:00.0)could be added by user on this cxl Bus. Link: [1]: https://lore.kernel.org/linux-cxl/20220616141950.23374-2-Jonathan.Cameron@h… [2]: https://edk2.groups.io/g/devel/topic/rfc_patch_0_1/108173029 Yuquan Wang (2): SbsaQemu: Add acpi0016 & acpi0017 objects into DSDT SbsaQemu: AcpiTables: Add CEDT Table Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 30 +- .../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 20 +- Silicon/Qemu/SbsaQemu/AcpiTables/Cedt.aslc | 70 +++ Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 410 +++++++++++++++++- Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc | 2 +- .../SbsaQemuPciHostBridgeLib.c | 4 +- .../SbsaQemuPciHostBridgeLib.inf | 3 + Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 34 +- 8 files changed, 555 insertions(+), 18 deletions(-) create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Cedt.aslc -- 2.34.1 信息安全声明：本邮件包含信息归发件人所在组织所有,发件人所在组织对该邮件拥有所有权利。请接收者注意保密,未经发件人书面许可,不得向任何第三方组织和个人透露本邮件所含信息。 Information Security Notice: The information contained in this mail is solely property of the sender's organization.This mail communication is confidential.Recipients named above are obligated to maintain secrecy and are not permitted to disclose the contents of this communication to others.

3 months, 3 weeks

1
0
0 0

How to run Hafnium under SbsaQemu

by xiongyining1480＠phytium.com.cn

Hello Marcin I’m sorry to disturb you in your busy schedule. Hafnium is the Secure Partition Manager (SPM) reference implementation. The documents describe that qemu above 2.9 version support to run hafnium, and I am thinking about how to run Hafnium under SbsaQemu, is there any demo or any reference? Yours sincerely yining

4 months, 2 weeks

2
1
0 0

No Sync meetings in July

by Marcin Juszkiewicz

I am going for vacations therefore there will be no sync meetings in July. Next one is on 13th August 2024.

5 months, 2 weeks

1
0
0 0

Post Linaro Connect MAD24 notes

by Marcin Juszkiewicz

Linaro Connect MAD24 brought several meetings and discussions. We had session where I presented what was done on SBSA Reference Platform during last year and what are plans. https://resources.linaro.org/en/resource/fnNt6vFpdT73EDhLZCxK6w has video (with AI generated subtitles) and slides. Current patch queue: QEMU: - move sbsa-ref to Neoverse-N2 by default - switch from OpenBSD to FreeBSD in QEMU CI (for non-Linux coverage) - update firmware used in QEMU CI to TF-A 2.11.0 + EDK2 stable202405 EDK2: - multiple PCIe buses in NUMA setup - update TF-A in edk2-non-osi to 2.11.0 like above Some of my notes and ideas from Connect below. 1. Simple topology stuff. Maybe instead of exporting whole /cpus/cpu-map/ we should export simple topology: cpus { topology { threads = <0x01>; cores = <0x04>; clusters = <0x01>; sockets = <0x01>; }; It gives everything we need. And much easier parsing in TF-A. Had some thinking about exporting amount of cores per cluster (8 now, virt uses 16 which is architecture maximum now) in case we would use it in generation of PPTT in EDK2. 2. L1/L2 cache info per core in PPTT. I was asked can we put L1/L2 cache information for each core in PPTT. We would need to change that code while handling topology stuff so why not do that at same time. It would be used once we get MPAM support. 3. Move to Neoverse-N2 by default. N2 is v9.0 cpu which gives us several features like RME, RNG, SVE etc enabled by default. There is a work related with CCA (Confidential Computing) which requires RME. Presence of RNG allows us to provide EFI_PROTOCOL_RNG to kernel. 4. EDK2 needs changes for SMCCC 1.5 ArmCallSmc*() functions make use of x0-x7 registers (x0-x7 as arguments, x0-x3 as results) like it was designed in 2016 in "SMC Calling Conventions" specification. But those calls can use x0-x17 (both as arguments and results) since 2020 and our topology stuff needs that. https://developer.arm.com/documentation/den0028/latest/ As part of it should also use ArmCallSmc() instead of ArmCallSmc[0-3]() functions - this way we can use more arguments/results without a need for creation of all ArmCallSmc[0-17]() calls. 5. Firmware Handoff protocol FH protocol is very simple protocol to share data between firmware layers. We could use it instead of Devicetree so people would stop suggesting 'add this or that to DT'. https://github.com/FirmwareHandoff/firmware_handoff We should do it sooner than later - 'adapt spec now, or adapt to spec later' kind. 6. CPU hotplug So far the only data is 'check with cpu hotplug, -smp and maxcpus stuff' but it may be interesting to know do we (can) have it or not. Any opinions? Something to add, comments?

6 months, 3 weeks

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MIPDR changes are coming

by Marcin Juszkiewicz

There is a patch for changing MPIDR_EL1 handling on qemu-devel ML [1] which (if merged) will force us to do changes to SBSA-ref in QEMU, TF-A and probably EDK2 too. 1. https://lore.kernel.org/qemu-devel/20240419183135.12276-1-dorjoychy111@gmai… Details: MPIDR_EL1 register keeps cpu topology information. There are 2 or 4 8bit fields called Aff0-Aff3. For now Aff0 and Aff1 are used in QEMU: Aff0 - keeps core number (8 cores per cluster) Aff1 - keeps cluster number The plan is to use 0/1 for cores below Neoverse-N1 and 0-3 on higher ones with Aff0 being 0 as it is used for threads which are forbidden in designed emulated by QEMU. So whole topology can be stored: Aff0 - thread Aff1 - core Aff2 - cluster Aff3 - socket What it means for us? First of all: platform version MAJOR bump. So we would have platform_version = 1.0 as virtual hardware changes force firmware changes. Second: TF-A freeze is coming. Would be good to not have to wait for November and 2.12 release. We need to drop sbsa_topology.c from TF-A as it assumes Aff0/1 way and errors out on Aff0-3 way. Generation of PPTT in EDK2 needs to be changed too. Good side is that we may drop DT/SMC way and read socket/cluster/core/thread from MPIDR_EL1 directly. To make things easier I would like to drop support for Cortex-A57/A72 from sbsa-ref. They have Aff0/1 only and would require special handling in firmware. We would need it anyway as people tend to use misc versions of QEMU but this way code will get less and less used. And v8.2 will be minimal version. Opinions?

7 months, 3 weeks

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BSA ACS is at 76/84 tests

by Marcin Juszkiewicz

BSA ACS run on SBSA Reference platform gives 8 skipped tests: 303 : Check SMMU Large Physical Addr Support 403 : Memory mapped timer check 404 : Generate Mem Mapped SYS Timer Intr 405 : Restore PE timer on PE wake up 505 : Wake from System Timer Int 606 : 16550 compatible UART 806 : Legacy int must be SPI & lvl-sensitive 817 : Check Direct Transl P2P Support 303 wants SMMU with LPA support but skips when cpu lacks it. 606 checks for 16550 UART, we have PL011 one (you need one of them) 403, 404, 405, 505 require memory mapped system timers which we do not have. But we have PE timer always on (test 402) so can ignore them. 806 is platform specific and needs to be populated by partners with system legacy irq map. 817 wants RP type device with P2P and ATS support. Skips if not present.

8 months, 2 weeks

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