Hi Lorenzo,
I have noticed you are in holiday on Nov,1st. I can switch the meeting to Nov 2nd if other people are free.
@Lorenzo,James,
Can we arrange Zhangfei’s questions( TLB missing impact the performance in vsva/ sva) as below in next meeting. Or can you help involve any other experts focus on this? Appreciated so much for your help here.
Thanks:) Joyce
在 2022年10月28日，上午8:00，linaro-open-discussions-request@op-lists.linaro.org 写道：
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- Re: Linaro-open-discussions Digest, Vol 25, Issue 3 (Zhangfei Gao)
Message: 1 Date: Thu, 27 Oct 2022 12:06:59 +0800 From: Zhangfei Gao zhangfei.gao@linaro.org Subject: [Linaro-open-discussions] Re: Linaro-open-discussions Digest, Vol 25, Issue 3 To: Joyce Qi joyce.qi@linaro.org, Lorenzo Pieralisi lorenzo.pieralisi@linaro.org, jean-philippe jean-philippe@linaro.org Cc: linaro-open-discussions@op-lists.linaro.org, linux@armlinux.org.uk Message-ID: 2fba7536-1475-4755-9084-a920addecc42@linaro.org Content-Type: text/plain; charset=utf-8; format=flowed
Hi, Lorenzo
When we debug vsva, sva on guest with 2-stage translation, we found tlb miss impact performance a lot, with Jean's help.
Currently we are using huge page feature in glibc to overcome this issue. With huge page, vsva in guest can achieve comparable performance as sva in host.
More details: https://docs.qq.com/doc/DRXlpQmpTSlBZTGZZ Will do some
Basically we are using two optimization methods/ host sva: using memset fist to overcome io page fault, since cpu alloc physical memory is much faster than smmu. guest vsva: using huge page to overcome tlbmiss.
The customer are asking whether (next version) silicon (smmu) can do some help to concur tlb miss issue or io page fault issue. If so, software can be simpler. Any suggestions?
Thanks
On 2022/10/20 下午8:47, Joyce Qi via Linaro-open-discussions wrote:
Hi Jonathan,Lorenzo,all,
Do we have any topic to sync on our LOD meeting next week?
Thanks:) Joyce
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