On Thu, 20 Oct 2022 16:06:05 +0100 James Morse james.morse@arm.com wrote:
Hello,
I have two small topics that are relevant to CXL:
- maintaining the UEFI memory map with hotplug memory (series in development, no ACPI changes needed)
- Cache invalidate for NVdimm unlock and erase (spec proposal which will need a customer)
Hi James,
Dan raised an "interesting" point... https://lore.kernel.org/all/6387ed1b67fb7_c957294dd@dwillia2-mobl3.amr.corp....
Dan is arguing that we are obliged to flush all caches on any changing of address decoders. So basically any case where the OS is setting up any CXL memory for access. That applies to hotplug of volatile memory, or any OS managed bring up (including all persistent memory as there isn't currently a good way to bring that up in firmware even if it is there at he beginning).
It's plausible that he is right though I've not thought about it in enough depth yet + need to talk it through with our architecture experts to make sure I'm not missing something. If he is, that cache invalidate proposal just became much higher priority.
Jonathan
These would only take about thirty minutes, unless we want to go into all the gory details of the first one. I don't think its worth having the meeting just for these.
I've not got to rebase the virtual cpu hotplug stuff - I've been busy turning the MPAM stuff around this week. (and I'm out next monday)
Thanks,
James
On 20/10/2022 13:47, Joyce Qi wrote:
Hi Jonathan,Lorenzo,all,
Do we have any topic to sync on our LOD meeting next week?
Thanks:) Joyce
在 2022年10月18日，上午8:00，linaro-open-discussions-request@op-lists.linaro.org 写道：
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- Re: Invitation: Linaro Open Discussions monthly meeting @ Wed 5 Oct 2022 19:00 - 20:00 (HKT) (linaro-open-discussions@op-lists.linaro.org) (Salil Mehta)
Message: 1 Date: Mon, 17 Oct 2022 16:12:26 +0000 From: Salil Mehta salil.mehta@huawei.com Subject: [Linaro-open-discussions] Re: Invitation: Linaro Open Discussions monthly meeting @ Wed 5 Oct 2022 19:00 - 20:00 (HKT) (linaro-open-discussions@op-lists.linaro.org) To: "joyce.qi@linaro.org" joyce.qi@linaro.org, "james.morse@arm.com" james.morse@arm.com Cc: "linaro-open-discussions@op-lists.linaro.org" linaro-open-discussions@op-lists.linaro.org, "lorenzo.pieralisi@linaro.org" lorenzo.pieralisi@linaro.org, "ilkka@os.amperecomputing.com" ilkka@os.amperecomputing.com, Jean-Philippe Brucker jean-philippe.brucker@arm.com, "salil.mehta@opnsrc.net" salil.mehta@opnsrc.net Message-ID: 12408d4c06604dd4bd8e017adf7e5fe6@huawei.com Content-Type: text/plain; charset="utf-8"
Hi James, As discussed in the meeting below are the repositories which you might want to have a look.
[1] Forward ported QEMU with some fixes was shared (by Salil) https://github.com/salil-mehta/qemu.git virt-cpuhp-armv8/rfc-v1-port29092022
[2] James Approach with online-capable and present==possible (some fixes) https://github.com/salil-mehta/linux.git virt-cpuhp-arm64/rfc-v2/jmorse-pres-eq-poss-cpu
[3] Variant of James approach with online-capable and conditionally present cpus https://github.com/salil-mehta/linux.git virt-cpuhp-arm64/rfc-v2/jmorse-variant-with-cond-present-cpu
I have also shared the LOD presentation with Joyce for uploading to the site.
Attachment: [1] Linaro Open Discussion Meeting Update - 05102022 - Salil_Mehta-fixed.pdf
Many thanks Salil
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