On Thu, 29 Apr 2021 15:17:36 +0000 Jonathan Cameron via Linaro-open-discussions linaro-open-discussions@op-lists.linaro.org wrote:
On Thu, 29 Apr 2021 15:25:38 +0100 Lorenzo Pieralisi lorenzo.pieralisi@arm.com wrote:
On Thu, Apr 29, 2021 at 09:50:06AM +0100, Jonathan Cameron wrote:
is not really working for me. If you have a command script to share it is welcome - looking forward to testing and reviewing the DOE patches.
I'm mostly running aarch64 emulated on top of x86 - I should sanity check it on KVM at somepoint.
I'm copy typing this across machines, so whilst I hope there are no typos there might be. I've stripped back my normal case (which has a big complex topology to try and hit corner cases...) First I'd suggest checking that have right EDK2 etc to bring up pxb with normal pci rp and a device.
qemu-system-aarch64 -M virt,nvdimm=on -m 4g,maxmem=8G,slots=2 -cpu max -smp 4 \ -kernel Image \ -drive if=non,file=full.qcow2,format=qcow2,id=hd \ -nographic -no-reboot -append 'earlycon root=/dev/vda2 fsck.mode=skip' \ -bios QEMU_EFI.fd \ #note this needs the pxb enablement patches -maybe upstream by now. -object memory-backend-ram,size=4G,id=mem0 \ -numa node,nodeid=0,cpus=0-3,memdev=mem0 \ -object memory-backend-file,id=cxl-meme1,share,mem-path=/tmp/cxltest.raw,size=2G,align=2G \ -device pxb-cxl,bus_nr=128,id=cxl1.1,uid=0,len-window-base=1,window-base[0]=0x4c0000000,memdev[0]=cxl-mem1 \ # above range just needs to not trample on anything. -device cxl-rp,bus=cxl1.1,id=root_port13,chassis=0,slot=1 \ -device cxl-type3,bus=root_port13,memdev=cxl-mem1,lsa=cxl-mem1,id=cxl-pmem0,size=2G
Done, thank you very much. Is there a commit base on top of which I can apply Dan's CXL port enumeration patches + your DOE series ?
Nope. Looks like I need to send out a rebase as some of Dan's other patches hit mainline. Just did the merge to see how bad it is and other than a goto label having disappeared (and a bunch of fuzz) seems to go in fairly cleanly.
I'm not sure which order the various Intel patches currently on list would apply in. I tried a few possible orders and got issues. Looks like they need to rebase as well.
Best of all mainline is booting on this setup mid merge window which is always a pleasant surprise :)
I'll wait to send the rebase until near the end or after the merge window. We'll probably still have some issues with merging until we have an order in which various series will merge.
I sent the updated DOE patches out today.
https://lore.kernel.org/linux-pci/20210524133938.2815206-1-Jonathan.Cameron@...
There is still a bit of merge mess if you also pick up Dan's Port series. I was waiting for that to merge, but as it seems to be going slowly I went ahead with the DOE update. There is a lot of churn in the CXL code at the moment.
Also, a highly dubious blog / setup guide can be found at: https://people.kernel.org/jic23/howto-test-cxl-enablement-on-arm64-using-qem...
May well eat babies.
Jonathan
J
Thanks a lot Jonathan, Lorenzo
Hmm. Perhaps I should just write a blog post and include all the random corners needed to get this up. Problem then is I'd actually have to figure out what some of the parts are doing having long forgotten the answer so might take a day or two.
In meantime we can carry on here.
J
Thanks, Lorenzo
I remember reading there is an IRC channel cxl related (#cxl @ OFTC ?) - if there is happy to switch to it rather than bothering you with these queries.
I tend to avoid IRC because of potential auditing issues (no logs) so email is the way to go.
Thanks a lot ! Lorenzo > As there are some US folks who are interested in this topic (but super busy), > can we do a straw poll of whether any of them can make a call on Monday? > > If not go for a more China/Europe friendly time? > > We had a few more topics brewing, but I'm not sure they will be in a state > to discuss next week (or to give anyone else time to think about them > in advance). > > Obviously good to touch on any updates to older topics as well if anyone > has any! > > Jonathan > > > > > > Lorenzo >