Back in May 2023, when we were handling versioning changes, I added set of SMC calls between TF-A and EDK2 to share hardware details (instead of parsing DeviceTree in EDK2).
I think that it is time to move forward and drop DeviceTree support from EDK2 completely.
# what for we use DT now?
There are few things we read from DT in EDK2 now:
- cpu count - cpu mpidr value - cpu numa node id - memory nodes (with numa node ids)
# initial code
I took a look at it, created some tickets [1] in Linaro Jira and wrote some initial code for checking cpu count (will send to ML).
1. https://linaro.atlassian.net/browse/SRCPC-156
# ideas for next steps
For mpidr/numa I have some ideas. I was thinking of adding function in sbsa_sip_svc.c which would count cpus (using code I already have) and then malloc() memory for cpu struct { id, mpidr, node_id } for each cpu. And similar for memory nodes: read DT, alloc structures, fill them.
When EDK2 does SMC call to get cpu data like mpidr/node_id code will go through allocated structures and return single data. Again, similar for memory nodes.
The funny part: DT is somewhere in memory during BL3*, we provide it for EDK2 at start of memory but I probably do something wrong when trying to access it during BL3*.
Current data gathering reads DT from BL2 memory before MMU kicks in.
# things for the future
Adding SPM would require additional calls. So far I only created ticket [2] for it without looking into details.
2. https://linaro.atlassian.net/browse/SRCPC-165
# call for opinions
What are your opinions about it? Ideas? Someone maybe already considered it?
We want to remove use of DeviceTree from EDK2. One of things EDK2 did was counting cpu cores. Now it gets that value via SMC call.
Change-Id: I1c7fc234ba90ba32433b6e4aa2cf127f26da00fd Signed-off-by: Marcin Juszkiewicz marcin.juszkiewicz@linaro.org --- plat/qemu/qemu_sbsa/sbsa_sip_svc.c | 45 ++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+)
diff --git a/plat/qemu/qemu_sbsa/sbsa_sip_svc.c b/plat/qemu/qemu_sbsa/sbsa_sip_svc.c index 05ebec472..587048c33 100644 --- a/plat/qemu/qemu_sbsa/sbsa_sip_svc.c +++ b/plat/qemu/qemu_sbsa/sbsa_sip_svc.c @@ -28,8 +28,12 @@ static int platform_version_minor; #define SIP_SVC_VERSION SIP_FUNCTION_ID(1) #define SIP_SVC_GET_GIC SIP_FUNCTION_ID(100) #define SIP_SVC_GET_GIC_ITS SIP_FUNCTION_ID(101) +#define SIP_SVC_GET_CPU_COUNT SIP_FUNCTION_ID(200)
static uint64_t gic_its_addr; +static uint64_t cpu_count; +static uint64_t dt_first_cpu_node_offset; +static uint64_t dt_first_cpu_node_size;
void sbsa_set_gic_bases(const uintptr_t gicd_base, const uintptr_t gicr_base); uintptr_t sbsa_get_gicd(void); @@ -38,6 +42,7 @@ uintptr_t sbsa_get_gicr(void); void read_platform_config_from_dt(void *dtb) { int node; + int prev; const fdt64_t *data; int err; uintptr_t gicd_base; @@ -91,6 +96,43 @@ void read_platform_config_from_dt(void *dtb) return; } INFO("GICI base = 0x%lx\n", gic_its_addr); + + /* + * QEMU gives us this DeviceTree node: + * + * cpus { + * #size-cells = <0x00>; + * #address-cells = <0x02>; + * + * cpu@0 { + * reg = <0x00 0x00>; + * }; + * + * cpu@1 { + * reg = <0x00 0x01>; + * }; + * }; + */ + node = fdt_path_offset(dtb, "/cpus"); + if (node < 0) { + cpu_count = 1; /* We have at least one in case of missing entry in DT */ + INFO("No /cpus nodes. Found %lx cpus\n", cpu_count); + return; + } + + prev = fdt_first_subnode(dtb, node); + dt_first_cpu_node_offset = prev; + + while (1) { + cpu_count++; + node = fdt_next_subnode(dtb, prev); + if (node < 0) { + break; + } + dt_first_cpu_node_size = node - prev; + prev = node; + } + INFO("Found %lx cpus\n", cpu_count); }
void read_platform_version(void *dtb) @@ -163,6 +205,9 @@ uintptr_t sbsa_sip_smc_handler(uint32_t smc_fid, case SIP_SVC_GET_GIC_ITS: SMC_RET2(handle, NULL, gic_its_addr);
+ case SIP_SVC_GET_CPU_COUNT: + SMC_RET2(handle, NULL, cpu_count); + default: ERROR("%s: unhandled SMC (0x%x) (function id: %d)\n", __func__, smc_fid, smc_fid - SIP_FUNCTION);
As part of removing DeviceTree use from EDK2 we moved counting of cpu cores to TF-A. Then SMC call gets value on platform initialization.
Reading MPIDR value for MADT table is broken - OS gets just one cpu. This gets sorted in separate patch.
Signed-off-by: Marcin Juszkiewicz marcin.juszkiewicz@linaro.org --- .../Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf | 1 + .../SbsaQemuPlatformDxe.inf | 1 + .../Include/IndustryStandard/SbsaQemuSmc.h | 1 + .../Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c | 6 +-- .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 8 +-- .../SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c | 10 ++++ .../Library/FdtHelperLib/FdtHelperLib.c | 49 ------------------- 7 files changed, 17 insertions(+), 59 deletions(-)
diff --git a/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf b/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf index a34f54d431d4..11277e226cdf 100644 --- a/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf +++ b/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf @@ -56,3 +56,4 @@ [Pcd] gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdChassisManufacturer gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdChassisAssetTag gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdChassisSKU + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf index 19534b7a274a..a0563f574b76 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf @@ -46,6 +46,7 @@ [Pcd] gArmTokenSpaceGuid.PcdGicDistributorBase gArmTokenSpaceGuid.PcdGicRedistributorsBase gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdGicItsBase + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount
[Depex] diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h index 7934875e4aba..3138de327367 100644 --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h @@ -14,5 +14,6 @@ #define SIP_SVC_VERSION SMC_SIP_FUNCTION_ID(1) #define SIP_SVC_GET_GIC SMC_SIP_FUNCTION_ID(100) #define SIP_SVC_GET_GIC_ITS SMC_SIP_FUNCTION_ID(101) +#define SIP_SVC_GET_CPU_COUNT SMC_SIP_FUNCTION_ID(200)
#endif /* SBSA_QEMU_SMC_H_ */ diff --git a/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c b/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c index c38f2851904f..56aad6d02388 100644 --- a/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c +++ b/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c @@ -33,7 +33,7 @@ OemIsProcessorPresent ( UINTN ProcessorIndex ) { - if (ProcessorIndex < FdtHelperCountCpus ()) { + if (ProcessorIndex < PcdGet32 (PcdCoreCount)) { return TRUE; }
@@ -76,7 +76,7 @@ OemGetProcessorInformation ( { UINT16 ProcessorCount;
- ProcessorCount = FdtHelperCountCpus (); + ProcessorCount = PcdGet32 (PcdCoreCount);
if (ProcessorIndex < ProcessorCount) { ProcessorStatus->Bits.CpuStatus = 1; // CPU enabled @@ -121,7 +121,7 @@ OemGetMaxProcessors ( VOID ) { - return FdtHelperCountCpus (); + return PcdGet32 (PcdCoreCount); }
/** Gets information about the cache at the specified cache level. diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c index 9fb17151d7b8..b59e999b23ce 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c @@ -255,7 +255,7 @@ AddMadtTable ( // Initialize GIC Redistributor Structure EFI_ACPI_6_0_GICR_STRUCTURE Gicr = SBSAQEMU_MADT_GICR_INIT();
- // Get CoreCount which was determined eariler after parsing device tree + // Get CoreCount which was determined earlier from TF-A NumCores = PcdGet32 (PcdCoreCount);
// Calculate the new table size based on the number of cores @@ -758,12 +758,6 @@ InitializeSbsaQemuAcpiDxe ( { EFI_STATUS Status; EFI_ACPI_TABLE_PROTOCOL *AcpiTable; - UINT32 NumCores; - - // Parse the device tree and get the number of CPUs - NumCores = FdtHelperCountCpus (); - Status = PcdSet32S (PcdCoreCount, NumCores); - ASSERT_RETURN_ERROR (Status);
// Check if ACPI Table Protocol has been installed Status = gBS->LocateProtocol ( diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c index 4ebbe7c93a19..cc2ac346e197 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c @@ -123,5 +123,15 @@ InitializeSbsaQemuPlatformDxe ( } }
+ SmcResult = ArmCallSmc0 (SIP_SVC_GET_CPU_COUNT, &Arg0, NULL, NULL); + if (SmcResult == SMC_ARCH_CALL_SUCCESS) { + Result = PcdSet32S (PcdCoreCount, Arg0); + ASSERT_RETURN_ERROR (Result); + } + + Arg0 = PcdGet32 (PcdCoreCount); + + DEBUG ((DEBUG_INFO, "We have %d cpus.\n", Arg0)); + return EFI_SUCCESS; } diff --git a/Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.c b/Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.c index 7fdfb055db76..822605a940ca 100644 --- a/Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.c +++ b/Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.c @@ -47,52 +47,3 @@ FdtHelperGetMpidr (
return (fdt64_to_cpu (ReadUnaligned64 (RegVal))); } - -/** Walks through the Device Tree created by Qemu and counts the number - of CPUs present in it. - - @return The number of CPUs present. -**/ -EFIAPI -UINT32 -FdtHelperCountCpus ( - VOID - ) -{ - VOID *DeviceTreeBase; - INT32 Node; - INT32 Prev; - INT32 CpuNode; - UINT32 CpuCount; - - DeviceTreeBase = (VOID *)(UINTN)PcdGet64 (PcdDeviceTreeBaseAddress); - ASSERT (DeviceTreeBase != NULL); - - // Make sure we have a valid device tree blob - ASSERT (fdt_check_header (DeviceTreeBase) == 0); - - CpuNode = fdt_path_offset (DeviceTreeBase, "/cpus"); - if (CpuNode <= 0) { - DEBUG ((DEBUG_ERROR, "Unable to locate /cpus in device tree\n")); - return 0; - } - - CpuCount = 0; - - // Walk through /cpus node and count the number of subnodes. - // The count of these subnodes corresponds to the number of - // CPUs created by Qemu. - Prev = fdt_first_subnode (DeviceTreeBase, CpuNode); - mFdtFirstCpuOffset = Prev; - while (1) { - CpuCount++; - Node = fdt_next_subnode (DeviceTreeBase, Prev); - if (Node < 0) { - break; - } - mFdtCpuNodeSize = Node - Prev; - Prev = Node; - } - - return CpuCount; -}
On Wed, 22 Nov 2023 at 11:20, Marcin Juszkiewicz marcin.juszkiewicz@linaro.org wrote:
As part of removing DeviceTree use from EDK2 we moved counting of cpu cores to TF-A. Then SMC call gets value on platform initialization.
Reading MPIDR value for MADT table is broken - OS gets just one cpu. This gets sorted in separate patch.
Signed-off-by: Marcin Juszkiewicz marcin.juszkiewicz@linaro.org
.../Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf | 1 + .../SbsaQemuPlatformDxe.inf | 1 + .../Include/IndustryStandard/SbsaQemuSmc.h | 1 + .../Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c | 6 +-- .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 8 +-- .../SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c | 10 ++++ .../Library/FdtHelperLib/FdtHelperLib.c | 49 -------------------
How are you ensuring that the PCD is set before it is read?
Generally, dynamic PCDs are not really suitable for this kind of thing. If there is a collection of data items that you receive from the secure firmware, it would be better to model this as a protocol, so that other drivers can DEPEX on it (i.e., the drivers that need this information will not be dispatched before the driver that exposes it)
7 files changed, 17 insertions(+), 59 deletions(-)
diff --git a/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf b/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf index a34f54d431d4..11277e226cdf 100644 --- a/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf +++ b/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf @@ -56,3 +56,4 @@ [Pcd] gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdChassisManufacturer gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdChassisAssetTag gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdChassisSKU
- gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf index 19534b7a274a..a0563f574b76 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf @@ -46,6 +46,7 @@ [Pcd] gArmTokenSpaceGuid.PcdGicDistributorBase gArmTokenSpaceGuid.PcdGicRedistributorsBase gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdGicItsBase
- gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount
[Depex] diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h index 7934875e4aba..3138de327367 100644 --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h @@ -14,5 +14,6 @@ #define SIP_SVC_VERSION SMC_SIP_FUNCTION_ID(1) #define SIP_SVC_GET_GIC SMC_SIP_FUNCTION_ID(100) #define SIP_SVC_GET_GIC_ITS SMC_SIP_FUNCTION_ID(101) +#define SIP_SVC_GET_CPU_COUNT SMC_SIP_FUNCTION_ID(200)
#endif /* SBSA_QEMU_SMC_H_ */ diff --git a/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c b/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c index c38f2851904f..56aad6d02388 100644 --- a/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c +++ b/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c @@ -33,7 +33,7 @@ OemIsProcessorPresent ( UINTN ProcessorIndex ) {
- if (ProcessorIndex < FdtHelperCountCpus ()) {
- if (ProcessorIndex < PcdGet32 (PcdCoreCount)) { return TRUE; }
@@ -76,7 +76,7 @@ OemGetProcessorInformation ( { UINT16 ProcessorCount;
- ProcessorCount = FdtHelperCountCpus ();
ProcessorCount = PcdGet32 (PcdCoreCount);
if (ProcessorIndex < ProcessorCount) { ProcessorStatus->Bits.CpuStatus = 1; // CPU enabled
@@ -121,7 +121,7 @@ OemGetMaxProcessors ( VOID ) {
- return FdtHelperCountCpus ();
- return PcdGet32 (PcdCoreCount);
}
/** Gets information about the cache at the specified cache level. diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c index 9fb17151d7b8..b59e999b23ce 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c @@ -255,7 +255,7 @@ AddMadtTable ( // Initialize GIC Redistributor Structure EFI_ACPI_6_0_GICR_STRUCTURE Gicr = SBSAQEMU_MADT_GICR_INIT();
- // Get CoreCount which was determined eariler after parsing device tree
// Get CoreCount which was determined earlier from TF-A NumCores = PcdGet32 (PcdCoreCount);
// Calculate the new table size based on the number of cores
@@ -758,12 +758,6 @@ InitializeSbsaQemuAcpiDxe ( { EFI_STATUS Status; EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
UINT32 NumCores;
// Parse the device tree and get the number of CPUs
NumCores = FdtHelperCountCpus ();
Status = PcdSet32S (PcdCoreCount, NumCores);
ASSERT_RETURN_ERROR (Status);
// Check if ACPI Table Protocol has been installed Status = gBS->LocateProtocol (
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c index 4ebbe7c93a19..cc2ac346e197 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c @@ -123,5 +123,15 @@ InitializeSbsaQemuPlatformDxe ( } }
- SmcResult = ArmCallSmc0 (SIP_SVC_GET_CPU_COUNT, &Arg0, NULL, NULL);
- if (SmcResult == SMC_ARCH_CALL_SUCCESS) {
- Result = PcdSet32S (PcdCoreCount, Arg0);
- ASSERT_RETURN_ERROR (Result);
- }
- Arg0 = PcdGet32 (PcdCoreCount);
- DEBUG ((DEBUG_INFO, "We have %d cpus.\n", Arg0));
- return EFI_SUCCESS;
} diff --git a/Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.c b/Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.c index 7fdfb055db76..822605a940ca 100644 --- a/Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.c +++ b/Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.c @@ -47,52 +47,3 @@ FdtHelperGetMpidr (
return (fdt64_to_cpu (ReadUnaligned64 (RegVal))); }
-/** Walks through the Device Tree created by Qemu and counts the number
- of CPUs present in it.
- @return The number of CPUs present.
-**/ -EFIAPI -UINT32 -FdtHelperCountCpus (
- VOID
- )
-{
- VOID *DeviceTreeBase;
- INT32 Node;
- INT32 Prev;
- INT32 CpuNode;
- UINT32 CpuCount;
- DeviceTreeBase = (VOID *)(UINTN)PcdGet64 (PcdDeviceTreeBaseAddress);
- ASSERT (DeviceTreeBase != NULL);
- // Make sure we have a valid device tree blob
- ASSERT (fdt_check_header (DeviceTreeBase) == 0);
- CpuNode = fdt_path_offset (DeviceTreeBase, "/cpus");
- if (CpuNode <= 0) {
- DEBUG ((DEBUG_ERROR, "Unable to locate /cpus in device tree\n"));
- return 0;
- }
- CpuCount = 0;
- // Walk through /cpus node and count the number of subnodes.
- // The count of these subnodes corresponds to the number of
- // CPUs created by Qemu.
- Prev = fdt_first_subnode (DeviceTreeBase, CpuNode);
- mFdtFirstCpuOffset = Prev;
- while (1) {
- CpuCount++;
- Node = fdt_next_subnode (DeviceTreeBase, Prev);
- if (Node < 0) {
break;- }
- mFdtCpuNodeSize = Node - Prev;
- Prev = Node;
- }
- return CpuCount;
-}
2.42.0
W dniu 28.11.2023 o 19:00, Ard Biesheuvel pisze:
On Wed, 22 Nov 2023 at 11:20, Marcin Juszkiewicz marcin.juszkiewicz@linaro.org wrote:
As part of removing DeviceTree use from EDK2 we moved counting of cpu cores to TF-A. Then SMC call gets value on platform initialization.
Reading MPIDR value for MADT table is broken - OS gets just one cpu. This gets sorted in separate patch.
Signed-off-by: Marcin Juszkiewiczmarcin.juszkiewicz@linaro.org
.../Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf | 1 + .../SbsaQemuPlatformDxe.inf | 1 + .../Include/IndustryStandard/SbsaQemuSmc.h | 1 + .../Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c | 6 +-- .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 8 +-- .../SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c | 10 ++++ .../Library/FdtHelperLib/FdtHelperLib.c | 49 -------------------
How are you ensuring that the PCD is set before it is read?
I assumed that SbsaQemuPlatformDxe is run first - that's the place where we get GIC and ITS data from TF-A for use in all other places. Not checked the order of how they are called.
Generally, dynamic PCDs are not really suitable for this kind of thing. If there is a collection of data items that you receive from the secure firmware, it would be better to model this as a protocol, so that other drivers can DEPEX on it (i.e., the drivers that need this information will not be dispatched before the driver that exposes it)
OK. I looked at code and noticed that there is a Pcd for it already so thought that setting it once and use would work.
-
Ard Biesheuvel -
Marcin Juszkiewicz