Hi Joyce,
I'll be in Shenzhen next week but should be able to dial in subject to overcoming a slightly different network.
If we can poke the following disconnect that would be very helpful - if it happens on list rather than needing to be discussed on the call that's absolutely fine.
It's a difference of opinion between Mark Rutland and Rob Herring (both ARM) about how to do device tree representation of multi thread cores and resulting shared L1 caches. We mostly care about this because we'd like to maintain same level of support in QEMU for ACPI (which has always handled this case) and DT.
This was try number 1 based on advice from Rob was to use multiple reg entries in a single cpu node (how the DT spec currently specifies it based on ancient power PC roots)
https://lore.kernel.org/linux-arm-kernel/20250110161057.445-1-alireza.sanaee... Mark suggested that we just do out of CPU node description as is done for every other level of cache because of the complexity of phandles pointing to the node.
Proposal of out of CPU node description. Rob not happy with this one. https://lore.kernel.org/all/20250129164855.676-1-alireza.sanaee@huawei.com/ https://lore.kernel.org/all/20250203120527.3534-1-alireza.sanaee@huawei.com/
Whilst I'm fairly sure Mark's concerns about references to the CPU node can be resolved with a few minor tweaks (a few properties may become arrays that are index rather than single element) we'd really like to have the two experts engaged in the same thread as so far it's been a case of alternate responses.
The other topic that is in my pile is the cache flushing by PA range work. I'm going to be working with our HQ team to ensure the design we put out for that is general enough over the next 2 weeks so we should have something to share after that. The remaining questions prior to posting an RFC are all low level detail things that I don't think would benefit from a discussion until we've shown the code.
Final potential topic is MPAM. Particularly if there is anything specific we can do to help with upstreaming.
Jonathan
Joyce Qi joyce.qi@linaro.org wrote:
Hi Jonathan，
Welcome to China and thanks for the detailed update！
@Rob，Mark
Welcome to join LOD discussion！
For Jonathan’s first topics：
How to do device tree representation of multi thread cores and resulting shared L1 caches.
Would you like to communicate in this email list or do we need a LOD meeting to reach an agreement?
@James，
For the MPAM upstream，any help needed for the upstream from Huawei or Linaro？
Thanks：） Joyce
Hi Mark, Rob,
https://lore.kernel.org/linux-arm-kernel/20250110161057.445-1-alireza.sanaee... to the LoD discussion email list! Maybe you have missed the formal email since the title is not so clear:)
Jonathan from Huawei wants to sync the about how to do device tree representation of multi thread cores and resulting shared L1 caches In this email list.
Can we discuss here to have a unified solution?
https://lore.kernel.org/linux-arm-kernel/20250110161057.445-1-alireza.sanaee...
Great thanks:) Joyce
linaro-open-discussions@op-lists.linaro.org
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Jonathan Cameron -
Joyce Qi