From: Jonathan Cameron Jonathan.Cameron@huawei.com

This is just for purposes of poking the CMA / SPDM code. What exactly the model in the driver looks like is still to be worked out.

Note the PROBE_FORCE_SYNCHRONOUS is a workaround to avoid warnings about trying to load an additional crypto module whilst doing an asychronous probe.

Signed-off-by: Jonathan Cameron Jonathan.Cameron@huawei.com --- drivers/cxl/Kconfig | 1 + drivers/cxl/cxlmem.h | 2 ++ drivers/cxl/pci.c | 19 ++++++++++++++++++- 3 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig index 9d53720bea07..4dfd2c19b285 100644 --- a/drivers/cxl/Kconfig +++ b/drivers/cxl/Kconfig @@ -17,6 +17,7 @@ config CXL_MEM tristate "CXL.mem: Memory Devices" default CXL_BUS select PCI_DOE_DRIVER + select PCI_CMA help The CXL.mem protocol allows a device to act as a provider of "System RAM" and/or "Persistent Memory" that is fully coherent diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h index d68da2610265..1a8c59864a95 100644 --- a/drivers/cxl/cxlmem.h +++ b/drivers/cxl/cxlmem.h @@ -125,6 +125,7 @@ struct cxl_mbox_cmd { * * @dev: The device associated with this CXL state * @cdat_doe: Auxiliary DOE device capabile of reading CDAT + * @cma_doe: Component measurement and authentication mailbox * @regs: Parsed register blocks * @payload_size: Size of space for payload * (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register) @@ -157,6 +158,7 @@ struct cxl_dev_state { struct device *dev;

struct pci_doe_dev *cdat_doe; + struct pci_doe_dev *cma_doe; struct cxl_regs regs;

size_t payload_size; diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 086532a42480..0f95f8b2b37b 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -1,9 +1,14 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright(c) 2020 Intel Corporation. All rights reserved. */ #include <linux/io-64-nonatomic-lo-hi.h> +//#include <uapi/linux/cxl_mem.h> +#include <linux/security.h> +#include <linux/pci-cma.h> +//#include <linux/debugfs.h> #include <linux/module.h> #include <linux/sizes.h> #include <linux/mutex.h> +#include <linux/spdm.h> #include <linux/list.h> #include <linux/pci.h> #include <linux/pci-doe.h> @@ -586,6 +591,9 @@ static int cxl_setup_doe_devices(struct cxl_dev_state *cxlds) if (pci_doe_supports_prot(new_dev, PCI_DVSEC_VENDOR_ID_CXL, CXL_DOE_PROTOCOL_TABLE_ACCESS)) cxlds->cdat_doe = new_dev; + if (pci_doe_supports_prot(new_dev, PCI_VENDOR_ID_PCI_SIG, + 1)) //hack + cxlds->cma_doe = new_dev;

next: pos = pci_find_next_ext_capability(pdev, pos, PCI_EXT_CAP_ID_DOE); @@ -681,6 +689,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) struct cxl_register_map map; struct cxl_memdev *cxlmd; struct cxl_dev_state *cxlds; + struct spdm_state spdm_state; int rc;

/* @@ -728,6 +737,14 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)

cxl_setup_cdat(cxlds);

+ /* CMA is optional - policy control will be needed */ + if (cxlds->cma_doe) { + pci_cma_init(cxlds->cma_doe, &spdm_state); + rc = pci_cma_authenticate(&spdm_state); + if (rc) + return rc; + } + cxlmd = devm_cxl_add_memdev(cxlds); if (IS_ERR(cxlmd)) return PTR_ERR(cxlmd); @@ -750,7 +767,7 @@ static struct pci_driver cxl_pci_driver = { .id_table = cxl_mem_pci_tbl, .probe = cxl_pci_probe, .driver = { - .probe_type = PROBE_PREFER_ASYNCHRONOUS, + .probe_type = PROBE_FORCE_SYNCHRONOUS, }, };