If a CPU isn't part of the class' affinity, skip onlining it. Otherwise, it will try to allocate a domain for it that will fault.
An example is when there are 2 memory MSCs with affinities to the first 64 CPUs (32 CPUs for each memory MSC) and 1 L3 cache MSC with affinity to the first 32 CPUs. When a call back to online CPU 63 for the second memory MSC is triggered, the function will first check the caches, and it will fault and return as CPU 63 is not part of the caches' affinity, without trying to check for the memory MSC. Thus, only 1 memory MSC will show up, even though there are 2 that could be managed.
Also skip when offlining a CPU that's not part of the class' affinity.
Signed-off-by: Hesham Almatary hesham.almatary@huawei.com --- drivers/platform/mpam/mpam_resctrl.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/platform/mpam/mpam_resctrl.c b/drivers/platform/mpam/mpam_resctrl.c index 471fb1a6c7e2..bfc25a8e4f03 100644 --- a/drivers/platform/mpam/mpam_resctrl.c +++ b/drivers/platform/mpam/mpam_resctrl.c @@ -1076,6 +1076,9 @@ int mpam_resctrl_online_cpu(unsigned int cpu) if (!res->class) continue; // dummy_resource;
+ if (!cpumask_test_cpu(cpu, &res->class->affinity)) + continue; // This CPU isn't part of the class' affinity; + dom = mpam_get_domain_from_cpu(cpu, res); if (dom) { cpumask_set_cpu(cpu, &dom->resctrl_dom.cpu_mask); @@ -1108,6 +1111,9 @@ int mpam_resctrl_offline_cpu(unsigned int cpu) if (!res->class) continue; // dummy resource
+ if (!cpumask_test_cpu(cpu, &res->class->affinity)) + continue; // This CPU isn't part of the class' affinity; + d = resctrl_get_domain_from_cpu(cpu, &res->resctrl_res); dom = container_of(d, struct mpam_resctrl_dom, resctrl_dom);
If there are 128 CPUs in the system, but there is one memory and/or cache MSC with affinity to a subset of these CPUs (e.g., 32 CPUs), caches/memories MSC won't be picked at all and nothing will appear in resctrl to manage valid MSCs.
This commit drops the assumption that caches or memory MSCs have affinity to the entire CPUs in the system.
Signed-off-by: Hesham Almatary hesham.almatary@huawei.com --- drivers/platform/mpam/mpam_resctrl.c | 8 -------- 1 file changed, 8 deletions(-)
diff --git a/drivers/platform/mpam/mpam_resctrl.c b/drivers/platform/mpam/mpam_resctrl.c index bfc25a8e4f03..667670597f38 100644 --- a/drivers/platform/mpam/mpam_resctrl.c +++ b/drivers/platform/mpam/mpam_resctrl.c @@ -613,11 +613,6 @@ static void mpam_resctrl_pick_caches(void) continue; }
- if (!cpumask_equal(&class->affinity, cpu_possible_mask)) { - pr_debug("pick_caches: Class has missing CPUs\n"); - continue; - } - /* Assume cache levels are the same size for all CPUs... */ cache_size = get_cpu_cacheinfo_size(smp_processor_id(), class->level); if (!cache_size) { @@ -658,9 +653,6 @@ static void mpam_resctrl_pick_mba(void) if (!class_has_usable_mba(cprops)) continue;
- if (!cpumask_equal(&class->affinity, cpu_possible_mask)) - continue; - /* * mba_sc reads the mbm_local counter, and waggles the MBA controls. * mbm_local is implicitly part of the L3, pick a resouce to be MBA
On Thu, 2 Feb 2023 10:21:49 +0000 Hesham Almatary via Linaro-open-discussions linaro-open-discussions@op-lists.linaro.org wrote:
Could probably use cpumask_subset() instead of cpumask_equal() here, if, design-wise, resctrl allows a class to have a subset of all possible CPUs.
If there are 128 CPUs in the system, but there is one memory and/or cache MSC with affinity to a subset of these CPUs (e.g., 32 CPUs), caches/memories MSC won't be picked at all and nothing will appear in resctrl to manage valid MSCs.
This commit drops the assumption that caches or memory MSCs have affinity to the entire CPUs in the system.
Signed-off-by: Hesham Almatary hesham.almatary@huawei.com
drivers/platform/mpam/mpam_resctrl.c | 8 -------- 1 file changed, 8 deletions(-)
diff --git a/drivers/platform/mpam/mpam_resctrl.c b/drivers/platform/mpam/mpam_resctrl.c index bfc25a8e4f03..667670597f38 100644 --- a/drivers/platform/mpam/mpam_resctrl.c +++ b/drivers/platform/mpam/mpam_resctrl.c @@ -613,11 +613,6 @@ static void mpam_resctrl_pick_caches(void) continue; }
if (!cpumask_equal(&class->affinity,
cpu_possible_mask)) {
pr_debug("pick_caches: Class has missing
CPUs\n");
continue;
}
- /* Assume cache levels are the same size for all
CPUs... */ cache_size = get_cpu_cacheinfo_size(smp_processor_id(), class->level); if (!cache_size) { @@ -658,9 +653,6 @@ static void mpam_resctrl_pick_mba(void) if (!class_has_usable_mba(cprops)) continue;
if (!cpumask_equal(&class->affinity,
cpu_possible_mask))
continue;
- /*
- mba_sc reads the mbm_local counter, and waggles
the MBA controls. * mbm_local is implicitly part of the L3, pick a resouce to be MBA
linaro-open-discussions@op-lists.linaro.org