Hi,
There has been some discussion on the card QEMU-414:
https://projects.linaro.org/browse/QEMU-414
about adding another CPU model to QEMU that is somewhat more advanced than the current v8.0 offerings but isn't quite the rolling "all the ARM you can eat" -cpu max. So far the primary interest I'm aware of has come from people working on the SBSA and BSA reference platforms who want to have something with a few more features than the base v8.0 spec which we have covered.
So far we have been mostly focused on adding architectural features that are of direct interest to kernel and user space developers. This has allowed testing of code that uses SVE, MTE and BTI instructions. However there are no real CPUs that have quite the "random" assortment of ARM features QEMU currently implements.
Implementing a new CPU model is not free either. We would have to back fill features we have currently skipped - some fairly simple and others not so much. We might also have to implement new on-chip devices (for example GICv4). We are also not interested in implementing a "only in QEMU" chip that has no real world analogue.
However to decide on real world chip to model we need to gather requirements about what is it potential users need in this model? What architectural features are most interesting and what real world chip meets them?
I would like to here any feedback and maybe this could be a topic for a future sync-up call?
W dniu 03.12.2020 o 22:21, Alex Bennée pisze:
There has been some discussion on the card QEMU-414:
https://projects.linaro.org/browse/QEMU-414
about adding another CPU model to QEMU that is somewhat more advanced than the current v8.0 offerings but isn't quite the rolling "all the ARM you can eat" -cpu max. So far the primary interest I'm aware of has come from people working on the SBSA and BSA reference platforms who want to have something with a few more features than the base v8.0 spec which we have covered.
So far we have been mostly focused on adding architectural features that are of direct interest to kernel and user space developers. This has allowed testing of code that uses SVE, MTE and BTI instructions. However there are no real CPUs that have quite the "random" assortment of ARM features QEMU currently implements.
Something like Cortex-A76/78 would be nice. v8.2 with RAS, VHE, VMID16, SMMUv3, PMUv3p1 etc.
Several features are required by either BSA or higher levels of SBSA specs. For example crypto (SHA3, SHA512, SM3, SM4), SVE, MTE or Pointer Authentication.
v8.5 added cache speculation side-channel attack migitations and they are required by BSA and SBSA level 6. They probably do not matter in QEMU but could be checked for existence.
BSA mentions CBSA specification but it is not public yet so no information what requirements it adds.
As any Arm licensee can choose which features they add to base v8.2 core I think that QEMU can have cortex-a76 with some selected features added on top (versioned or not - depends on QEMU devs decision).
I attached HTML table with BSA and SBSA requirements which may be helpful with finding out which cpu/system features are required by specifications. It will be updated once CBSA gets published (or any new similar spec).
Implementing a new CPU model is not free either. We would have to back fill features we have currently skipped - some fairly simple and others not so much. We might also have to implement new on-chip devices (for example GICv4). We are also not interested in implementing a "only in QEMU" chip that has no real world analogue. > However to decide on real world chip to model we need to gather requirements about what is it potential users need in this model? What architectural features are most interesting and what real world chip meets them?
SBSA Level 4 requires v8.3, SMMU v3 and GIC v3. Next levels bump CPU to v8.4/8.5 and SMMU to v3.2 while keeping GIC at v3.
BSA also mentions only GIC v2/v2m/v3.
In addition,we would like to emphasize the Neoverse N1/N2 support and SVE/SVE2 support to be considered on priority.This is to cater to the various applications/use-cases targeted in HPC,AI and server applications.
On Dec 7 2020, at 4:31 am, Marcin Juszkiewicz marcin.juszkiewicz@linaro.org wrote:
W dniu 03.12.2020 o 22:21, Alex Bennée pisze:
There has been some discussion on the card QEMU-414: https://projects.linaro.org/browse/QEMU-414 about adding another CPU model to QEMU that is somewhat more advanced than the current v8.0 offerings but isn't quite the rolling "all the ARM you can eat" -cpu max. So far the primary interest I'm aware of has come from people working on the SBSA and BSA reference platforms who want to have something with a few more features than the base v8.0 spec which we have covered.
So far we have been mostly focused on adding architectural features that are of direct interest to kernel and user space developers. This has allowed testing of code that uses SVE, MTE and BTI instructions. However there are no real CPUs that have quite the "random" assortment of ARM features QEMU currently implements.
Something like Cortex-A76/78 would be nice. v8.2 with RAS, VHE, VMID16, SMMUv3, PMUv3p1 etc.
Several features are required by either BSA or higher levels of SBSA specs. For example crypto (SHA3, SHA512, SM3, SM4), SVE, MTE or Pointer Authentication.
v8.5 added cache speculation side-channel attack migitations and they are required by BSA and SBSA level 6. They probably do not matter in QEMU but could be checked for existence.
BSA mentions CBSA specification but it is not public yet so no information what requirements it adds.
As any Arm licensee can choose which features they add to base v8.2 core I think that QEMU can have cortex-a76 with some selected features added on top (versioned or not - depends on QEMU devs decision).
I attached HTML table with BSA and SBSA requirements which may be helpful with finding out which cpu/system features are required by specifications. It will be updated once CBSA gets published (or any new similar spec).
Implementing a new CPU model is not free either. We would have to back fill features we have currently skipped - some fairly simple and others not so much. We might also have to implement new on-chip devices (for example GICv4). We are also not interested in implementing a "only in QEMU" chip that has no real world analogue. > However to decide on real world chip to model we need to gather requirements about what is it potential users need in this model? What architectural features are most interesting and what real world chip meets them?
SBSA Level 4 requires v8.3, SMMU v3 and GIC v3. Next levels bump CPU to v8.4/8.5 and SMMU to v3.2 while keeping GIC at v3.
BSA also mentions only GIC v2/v2m/v3.
Alex Bennée alex.bennee@linaro.org writes:
Hi,
There has been some discussion on the card QEMU-414:
<snip>
I would like to here any feedback and maybe this could be a topic for a future sync-up call?
I have set-up a call for Friday:
https://calendar.google.com/event?action=TEMPLATE&tmeid=NG11c3Y1YXBwMmlj...
all those interested are welcome.
linaro-open-discussions@op-lists.linaro.org
-
Alex Bennée -
Marcin Juszkiewicz -
Shashi Mallela