Hi all，
Since no feedback yet，I think maybe it’s still Easter Holiday so will cancel today’s meeting.
Thanks Joyce
On 21 Apr 2025, at 09:36, Joyce Qi joyce.qi@linaro.org wrote:
Hi Jonathan,
Do we have any topic for this Tuesday’s LOD meeting?
Hi Mark, Rob,
Do you have time to look at handle multiple threads in ARM cpu node issue?
Thanks Joyce
On 25 Mar 2025, at 19:24, Joyce Qi joyce.qi@linaro.org wrote:
Hi Mark, Rob,
https://lore.kernel.org/linux-arm-kernel/20250110161057.445-1-alireza.sanaee... to the LoD discussion email list! Maybe you have missed the formal email since the title is not so clear:)
Jonathan from Huawei wants to sync the about how to do device tree representation of multi thread cores and resulting shared L1 caches In this email list.
Can we discuss here to have a unified solution?
https://lore.kernel.org/linux-arm-kernel/20250110161057.445-1-alireza.sanaee...
Great thanks:) Joyce
On 21 Feb 2025, at 18:07, Jonathan Cameron jonathan.cameron@huawei.com wrote:
Hi Joyce,
I'll be in Shenzhen next week but should be able to dial in subject to overcoming a slightly different network.
If we can poke the following disconnect that would be very helpful
- if it happens on list rather than needing to be discussed on the call
that's absolutely fine.
It's a difference of opinion between Mark Rutland and Rob Herring (both ARM) about how to do device tree representation of multi thread cores and resulting shared L1 caches. We mostly care about this because we'd like to maintain same level of support in QEMU for ACPI (which has always handled this case) and DT.
This was try number 1 based on advice from Rob was to use multiple reg entries in a single cpu node (how the DT spec currently specifies it based on ancient power PC roots)
https://lore.kernel.org/linux-arm-kernel/20250110161057.445-1-alireza.sanaee... Mark suggested that we just do out of CPU node description as is done for every other level of cache because of the complexity of phandles pointing to the node.
Proposal of out of CPU node description. Rob not happy with this one. https://lore.kernel.org/all/20250129164855.676-1-alireza.sanaee@huawei.com/ https://lore.kernel.org/all/20250203120527.3534-1-alireza.sanaee@huawei.com/
Whilst I'm fairly sure Mark's concerns about references to the CPU node can be resolved with a few minor tweaks (a few properties may become arrays that are index rather than single element) we'd really like to have the two experts engaged in the same thread as so far it's been a case of alternate responses.
The other topic that is in my pile is the cache flushing by PA range work. I'm going to be working with our HQ team to ensure the design we put out for that is general enough over the next 2 weeks so we should have something to share after that. The remaining questions prior to posting an RFC are all low level detail things that I don't think would benefit from a discussion until we've shown the code.
Final potential topic is MPAM. Particularly if there is anything specific we can do to help with upstreaming.
Jonathan
Joyce Qi joyce.qi@linaro.org wrote:
Hi Jonathan, all,
Happy New Year to all!
Do we have any topic to sync next week?
Thanks:) Joyce
On 27 Nov 2024, at 08:00, linaro-open-discussions-request@op-lists.linaro.org wrote:
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Today's Topics:
- Re: Flush by PA range Designs. (was Re: Linaro-open-discussions Digest, Vol 38, Issue 14) (Joyce Qi)
Message: 1 Date: Tue, 26 Nov 2024 18:36:22 +0800 From: Joyce Qi joyce.qi@linaro.org Subject: [Linaro-open-discussions] Re: Flush by PA range Designs. (was Re: Linaro-open-discussions Digest, Vol 38, Issue 14) To: James Morse james.morse@arm.com Cc: Jonathan Cameron Jonathan.Cameron@Huawei.com, James Morse via Linaro-open-discussions linaro-open-discussions@op-lists.linaro.org, linuxarm@huawei.com, zengheng4@huawei.com, wangyushan12@huawei.com, Dave Martin Dave.Martin@arm.com Message-ID: 5BF890F5-CE52-4682-AFE6-9FBDE56F2247@linaro.org Content-Type: text/plain; charset=utf-8
Hi all，
Will cancel today’s meeting since no special topic today, welcome to contact with when needed.
Thanks Joyce
On 25 Nov 2024, at 21:01, Joyce Qi joyce.qi@linaro.org wrote:
Hi Jonathan，
Would you like to continue the MPAM， Flush by PA range Designs or any other topics during tomorrow’s LOD meeting？
Thanks Joyce
> On 24 Oct 2024, at 00:14, James Morse james.morse@arm.com wrote: > > Hi guys, > > (CC: +Dave Martin) > > On 10/21/24 15:01, Joyce Qi wrote: >>> On 21 Oct 2024, at 20:50, James Morse james.morse@arm.com wrote: >>> On 21/10/2024 11:00, Joyce Qi via Linaro-open-discussions wrote: >>>> Thanks a lot for the detailed description and document sharing. >>>> I have uploaded the MPAM materials to the LOD Confluence. >>>> >>>> https://linaro.atlassian.net/wiki/spaces/LOD/overview%EF%BF%BC > >>>> Are you available to join tomorrow’s LoD meeting for the MPAM topics ? > > The code already published for something like the intPARTID proposal is here: > https://git.gitlab.arm.com/linux-arm/linux-dm/-/commits/mpam/partid-pmg-rema... > > The aim was to keep it within the MPAM driver, initially based on some static configuration to prove > its useful before making it more dynamic, probably a mount option. > > > Thanks, > > James
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