From: Joyce Qi [mailto:joyce.qi@linaro.org] Sent: Monday, October 31, 2022 12:31 PM To: Lorenzo Pieralisi lorenzo.pieralisi@linaro.org Cc: James Morse james.morse@arm.com; Jonathan Cameron via Linaro-open-discussions linaro-open-discussions@op-lists.linaro.org; Zhangfei Gao zhangfei.gao@linaro.org; Jonathan Cameron jonathan.cameron@huawei.com; Salil Mehta salil.mehta@huawei.com Subject: Re: Linaro-open-discussions Digest, Vol 25, Issue 9
Hi James, Lorenzo,
Thanks for recommendation and feedback.
Since both of you are the key person for the meeting. So how about starting from Nov 2nd, 13:30 CET time?
13:30~14:00, James can talk about vCPU Hotplug topic 14:00~14:30 Lorenzo can attend Zhangfei’s topic.
Does the time work for everyone?
or we can postpone the meeting to Nov, 8th?
I am okay with any of these times.
@jonathan, shameer, could you please confirm your availability?
Thanks Salil
在 2022年10月31日，下午4:42，Lorenzo Pieralisi lorenzo.pieralisi@linaro.org
写道：
On Fri, Oct 28, 2022 at 04:15:15PM +0100, James Morse wrote:
Hi Joyce,
I have meetings between 14:00 and 16:30 UK time on November the 2nd. 13:00
and 17:00 are
free if that day is better for everyone else...
I can do Wednesday November 2nd at 14:00 CET - if for anyone else tomorrow (Nov 1st) is better you should go ahead with the current setting and I will catch up with the recordings.
Lorenzo
On Zhangfei's question, I think you need Lorenzo and/or Jean, who I assume
have the
context to this.
Thanks,
James
On 28/10/2022 15:14, Joyce Qi wrote:
Hi Lorenzo,
I have noticed you are in holiday on Nov,1st. I can switch the meeting to
Nov 2nd if other people are free.
@Lorenzo,James,
Can we arrange Zhangfei’s questions( TLB missing impact the performance
in vsva/ sva) as below in next meeting.
Or can you help involve any other experts focus on this? Appreciated so much
for your help here.
Thanks:) Joyce
在 2022年10月28日，上午8:00，
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Today's Topics:
- Re: Linaro-open-discussions Digest, Vol 25, Issue 3 (Zhangfei Gao)
Message: 1 Date: Thu, 27 Oct 2022 12:06:59 +0800 From: Zhangfei Gao zhangfei.gao@linaro.org Subject: [Linaro-open-discussions] Re: Linaro-open-discussions Digest, Vol 25, Issue 3 To: Joyce Qi joyce.qi@linaro.org, Lorenzo Pieralisi lorenzo.pieralisi@linaro.org, jean-philippe jean-philippe@linaro.org Cc: linaro-open-discussions@op-lists.linaro.org, linux@armlinux.org.uk Message-ID: 2fba7536-1475-4755-9084-a920addecc42@linaro.org Content-Type: text/plain; charset=utf-8; format=flowed
Hi, Lorenzo
When we debug vsva, sva on guest with 2-stage translation, we found tlb miss impact performance a lot, with Jean's help.
Currently we are using huge page feature in glibc to overcome this issue. With huge page, vsva in guest can achieve comparable performance as sva in host.
More details: https://docs.qq.com/doc/DRXlpQmpTSlBZTGZZ Will do some
Basically we are using two optimization methods/ host sva: using memset fist to overcome io page fault, since cpu alloc physical memory is much faster than smmu. guest vsva: using huge page to overcome tlbmiss.
The customer are asking whether (next version) silicon (smmu) can do some help to concur tlb miss issue or io page fault issue. If so, software can be simpler. Any suggestions?
Thanks
On 2022/10/20 下午8:47, Joyce Qi via Linaro-open-discussions wrote:
Hi Jonathan,Lorenzo,all,
Do we have any topic to sync on our LOD meeting next week?
Thanks:) Joyce
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End of Linaro-open-discussions Digest, Vol 25, Issue 9