- Linaro-open-discussions - op-lists.linaro.org

by Lorenzo Pieralisi

Hi, I can't make February 22nd next week for LOD, I would kindly ask you please to reschedule the call from Feb 23rd onwards. I don't have any major update either, other than IORT specs as already mentioned on the mailing list. Thank you, Lorenzo

2 years, 10 months

2
1
0 0

Linaro OP-TEE Contribution (LOC) monthly meeting January 2022

by Ruchika Gupta

Hi, OP-TEE Contributions (LOC) monthly meeting is planned for Thursday Jan 27 @16.00 (UTC). If you have any topics you'd like to discuss, please let us know and we can schedule them. Meeting details: --------------- Date/time: January 27(a)16.00 (UTC) https://everytimezone.com/s/c3460919 Connection details: https://www.trustedfirmware.org/meetings/ Meeting notes: http://bit.ly/loc-notes Regards, Ruchika on behalf of the Linaro OP-TEE team

2 years, 11 months

1
1
0 0

Linaro open discussions call Jan 2022

by Jonathan Cameron

Hi Lorenzo, Starting a new thread as your previous reply disappeared somewhere deep in my email due to threading. > I would like to ask two things: > > - IORT: with new spec published, I believe Shameer should be able to > bring the RMR work to completion. We can have a quick chat about this. Shameer is keen to discuss this as well. > - Virt CPU hotplug: we should split the work - ie who is preparing and > posting kernel patches ? Salil is currently on leave but we can talk about the general approach / division of labor. I did a forward port of the QEMU side of things before Xmas but got distracted so haven't tested it yet. > > Please let me know if we can sync this month. One other topic request from us is for any updates on MPAM plan and if there is anything we can do to assist on that. Great to hear you had some success with the DOE/SPDM stuff. I've been head down in getting upstreamable CXL/qemu support sorted out so not looked at that stuff yet this year. Joyce, please could you organize for a Linaro Open Discussions call? Personally Tuesday / Thursday / Friday (UK time) mornings next week would work well, but we might need a poll to find a slot that works for everyone. Thanks, Jonathan

2 years, 11 months

3
5
0 0

[PATCH 00/10] Rebase of DOE patches plus the basic CMA support on top

by Jonathan Cameron

For sharing with Lorenzo. I'm holding off on posting the CMA patches until the open question around DOE / auxiliary bus is resolved. Not clear if we'll end up back where we started. Note that other than the devm_ fix patch I've not tweaked the DOE series for review comments. Base is cxl/next 53989fad1286e652ea3655ae3367ba698da8d2ff (the tree might have moved again in the meantime) Ira Weiny (1): cxl/cdat: Parse out DSMAS data from CDAT table Jonathan Cameron (9): PCI: Add vendor ID for the PCI SIG PCI/DOE: Add Data Object Exchange Aux Driver cxl/pci: Add DOE Auxiliary Devices cxl/mem: Add CDAT table reading from DOE lib/asn1_encoder: Add a function to encode many byte integer values. spdm: Introduce a library for DMTF SPDM PCI/CMA: Initial support for Component Measurement and Authentication ECN cxl/pci: Add really basic CMA authentication support. cxl: Fixes for wrong device in devm_ calls. drivers/cxl/Kconfig | 2 + drivers/cxl/cdat.h | 81 +++ drivers/cxl/core/memdev.c | 157 +++++ drivers/cxl/cxl.h | 10 + drivers/cxl/cxlmem.h | 50 ++ drivers/cxl/pci.c | 231 ++++++- drivers/pci/Kconfig | 19 + drivers/pci/Makefile | 5 + drivers/pci/cma.c | 105 +++ drivers/pci/doe.c | 701 +++++++++++++++++++ include/linux/asn1_encoder.h | 3 + include/linux/pci-cma.h | 19 + include/linux/pci-doe.h | 63 ++ include/linux/pci_ids.h | 1 + include/linux/spdm.h | 104 +++ include/uapi/linux/pci_regs.h | 29 +- lib/Kconfig | 3 + lib/Makefile | 2 + lib/asn1_encoder.c | 54 ++ lib/spdm.c | 1196 +++++++++++++++++++++++++++++++++ 20 files changed, 2833 insertions(+), 2 deletions(-) create mode 100644 drivers/cxl/cdat.h create mode 100644 drivers/pci/cma.c create mode 100644 drivers/pci/doe.c create mode 100644 include/linux/pci-cma.h create mode 100644 include/linux/pci-doe.h create mode 100644 include/linux/spdm.h create mode 100644 lib/spdm.c -- 2.32.0

2 years, 11 months

3
9
0 0

Linaro OP-TEE Contributions (LOC) monthly meeting - Dec 23 CANCELLED

by Ruchika Gupta

Hi, In light of the holiday season we are not expecting too many joiners on Dec 23. Hence, let's cancel the LOC (Linaro OP-TEE Contribution) monthly meeting scheduled for next week. Wish you all a great holiday and a happy new year. The next scheduled meeting will be on 27th January 2022. Regards, Ruchika (On behalf of OP-TEE team)

3 years

1
0
0 0

SCMI perf-domain protocol for DVFS

by Ulf Hansson

Hi all, This email intends to ask for potential interest in extending the support for the SCMI perf-domain protocol in the Linux kernel and in the firmware. Please, feel free to ignore this, while a short answer like "sounds interesting" would be sufficient information at this point. Some more details below. Today, the current support in the Linux kernel for the SCMI perf-domain protocol, is limited to be used for CPU frequency scaling, through the cpufreq subsystem. However, the SCMI perf-domain protocol isn't really limited to CPUs, but fits well for other generic peripheral devices too. By extending the support, we can avoid the need for SoC specific protocols/interfaces, while scaling performance for non-CPU devices. >From the Linux kernel point of view, we already have generic support for DVFS (Dynamic Voltage Frequency Scaling), through a mixture of subsystems/libraries. Without going into details, we should be able to tap into these existing infrastructures, to add support for the SCMI perf-protocol. In this way, the support would be generic and nicely abstracted from lower layer drivers/subsystems. Thoughts? Kind regards Ulf Hansson, Linaro Kernel Team

3 years

2
3
0 0

[PATCH v2 0/2] Wake task within the same cluster of waker if

by Yicong Yang

This is the follow-up work to support cluster scheduler. Previously we have added cluster level in the scheduler[1] to make tasks spread between clusters to bring more memory bandwidth and decrease cache contention. But it may hurt some workloads which are sensitive to the communication latency as they will be placed across clusters. We modified the select_idle_cpu() on the wake affine path in this series, expecting the wake affined task to be woken more likely on the same cluster with the waker. The latency will be decreased as the waker and wakee in the same cluster may benefit from the hot L3 cache tag. [1] https://lore.kernel.org/lkml/20210924085104.44806-1-21cnbao@gmail.com/ Hi Tim and Barry, This the modified patch of packing path of cluster scheduler and tests have been done on Kunpeng 920 2-socket 4-NUMA 128core platform, with 8 clusters on each NUMA. Patches based on 5.16-rc1. Compared to the previous one[2], we give up scanning the first cpu of the cluster as the cpu id may not be continuous. So we pickup the way of scanning cluster first before LLC. The result from tbench and pgbench are rather positive. [2] https://op-lists.linaro.org/pipermail/linaro-open-discussions/2021-October/… Barry Song (2): sched: Add per_cpu cluster domain info sched/fair: Scan cluster before scanning LLC in wake-up path include/linux/sched/sd_flags.h | 9 ++++++++ include/linux/sched/topology.h | 2 +- kernel/sched/fair.c | 41 +++++++++++++++++++++++++++++++++- kernel/sched/sched.h | 1 + kernel/sched/topology.c | 5 +++++ 5 files changed, 56 insertions(+), 2 deletions(-) -- 2.33.0

3 years, 1 month

2
4
0 0

[PATCH 10/10] cxl: Fixes for wrong device in devm_ calls.

by Jonathan Cameron

This prevents probing of the new cxl_mem driver as the device already has devres entries before probe. Signed-off-by: Jonathan Cameron <jonathan.cameron(a)huawei.com> --- drivers/cxl/core/memdev.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c index 95d710e80df0..129251ac5bd0 100644 --- a/drivers/cxl/core/memdev.c +++ b/drivers/cxl/core/memdev.c @@ -339,7 +339,7 @@ static bool cdat_hdr_valid(struct cxl_memdev *cxlmd) return check == 0; } -static int parse_dsmas(struct cxl_memdev *cxlmd) +static int parse_dsmas(struct cxl_memdev *cxlmd, struct device *dev) { struct cxl_dsmas *dsmas_ary = NULL; u32 *data = cxlmd->cdat_table; @@ -405,7 +405,7 @@ static int parse_dsmas(struct cxl_memdev *cxlmd) dev_dbg(&cxlmd->dev, "Found %d DSMAS entries\n", nr_dsmas); dsmas_byte_size = sizeof(*dsmas_ary) * nr_dsmas; - cxlmd->dsmas_ary = devm_kzalloc(&cxlmd->dev, dsmas_byte_size, GFP_KERNEL); + cxlmd->dsmas_ary = devm_kzalloc(dev, dsmas_byte_size, GFP_KERNEL); if (!cxlmd->dsmas_ary) { rc = -ENOMEM; goto free_dsmas; @@ -437,7 +437,7 @@ struct cxl_memdev *devm_cxl_add_memdev(struct cxl_dev_state *cxlds) /* Cache the data early to ensure is_visible() works */ if (!cxl_mem_cdat_get_length(cxlds, &cxlmd->cdat_length)) { - cxlmd->cdat_table = devm_kzalloc(dev, cxlmd->cdat_length, GFP_KERNEL); + cxlmd->cdat_table = devm_kzalloc(cxlds->dev, cxlmd->cdat_length, GFP_KERNEL); if (!cxlmd->cdat_table) { rc = -ENOMEM; goto err; @@ -445,7 +445,7 @@ struct cxl_memdev *devm_cxl_add_memdev(struct cxl_dev_state *cxlds) cxl_mem_cdat_read_table(cxlds, cxlmd->cdat_table, cxlmd->cdat_length); } - rc = parse_dsmas(cxlmd); + rc = parse_dsmas(cxlmd, cxlds->dev); if (rc) dev_err(dev, "No DSMAS data found: %d\n", rc); -- 2.32.0

3 years, 1 month

1
0
0 0

[PATCH 09/10] cxl/pci: Add really basic CMA authentication support.

by Jonathan Cameron

From: Jonathan Cameron <Jonathan.Cameron(a)huawei.com> This is just for purposes of poking the CMA / SPDM code. What exactly the model in the driver looks like is still to be worked out. Note the PROBE_FORCE_SYNCHRONOUS is a workaround to avoid warnings about trying to load an additional crypto module whilst doing an asychronous probe. Signed-off-by: Jonathan Cameron <Jonathan.Cameron(a)huawei.com> --- drivers/cxl/Kconfig | 1 + drivers/cxl/cxlmem.h | 2 ++ drivers/cxl/pci.c | 19 ++++++++++++++++++- 3 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig index 9d53720bea07..4dfd2c19b285 100644 --- a/drivers/cxl/Kconfig +++ b/drivers/cxl/Kconfig @@ -17,6 +17,7 @@ config CXL_MEM tristate "CXL.mem: Memory Devices" default CXL_BUS select PCI_DOE_DRIVER + select PCI_CMA help The CXL.mem protocol allows a device to act as a provider of "System RAM" and/or "Persistent Memory" that is fully coherent diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h index d68da2610265..1a8c59864a95 100644 --- a/drivers/cxl/cxlmem.h +++ b/drivers/cxl/cxlmem.h @@ -125,6 +125,7 @@ struct cxl_mbox_cmd { * * @dev: The device associated with this CXL state * @cdat_doe: Auxiliary DOE device capabile of reading CDAT + * @cma_doe: Component measurement and authentication mailbox * @regs: Parsed register blocks * @payload_size: Size of space for payload * (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register) @@ -157,6 +158,7 @@ struct cxl_dev_state { struct device *dev; struct pci_doe_dev *cdat_doe; + struct pci_doe_dev *cma_doe; struct cxl_regs regs; size_t payload_size; diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 086532a42480..0f95f8b2b37b 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -1,9 +1,14 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright(c) 2020 Intel Corporation. All rights reserved. */ #include <linux/io-64-nonatomic-lo-hi.h> +//#include <uapi/linux/cxl_mem.h> +#include <linux/security.h> +#include <linux/pci-cma.h> +//#include <linux/debugfs.h> #include <linux/module.h> #include <linux/sizes.h> #include <linux/mutex.h> +#include <linux/spdm.h> #include <linux/list.h> #include <linux/pci.h> #include <linux/pci-doe.h> @@ -586,6 +591,9 @@ static int cxl_setup_doe_devices(struct cxl_dev_state *cxlds) if (pci_doe_supports_prot(new_dev, PCI_DVSEC_VENDOR_ID_CXL, CXL_DOE_PROTOCOL_TABLE_ACCESS)) cxlds->cdat_doe = new_dev; + if (pci_doe_supports_prot(new_dev, PCI_VENDOR_ID_PCI_SIG, + 1)) //hack + cxlds->cma_doe = new_dev; next: pos = pci_find_next_ext_capability(pdev, pos, PCI_EXT_CAP_ID_DOE); @@ -681,6 +689,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) struct cxl_register_map map; struct cxl_memdev *cxlmd; struct cxl_dev_state *cxlds; + struct spdm_state spdm_state; int rc; /* @@ -728,6 +737,14 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) cxl_setup_cdat(cxlds); + /* CMA is optional - policy control will be needed */ + if (cxlds->cma_doe) { + pci_cma_init(cxlds->cma_doe, &spdm_state); + rc = pci_cma_authenticate(&spdm_state); + if (rc) + return rc; + } + cxlmd = devm_cxl_add_memdev(cxlds); if (IS_ERR(cxlmd)) return PTR_ERR(cxlmd); @@ -750,7 +767,7 @@ static struct pci_driver cxl_pci_driver = { .id_table = cxl_mem_pci_tbl, .probe = cxl_pci_probe, .driver = { - .probe_type = PROBE_PREFER_ASYNCHRONOUS, + .probe_type = PROBE_FORCE_SYNCHRONOUS, }, }; -- 2.32.0

3 years, 1 month

1
0
0 0

[PATCH 08/10] PCI/CMA: Initial support for Component Measurement and Authentication ECN

by Jonathan Cameron

From: Jonathan Cameron <Jonathan.Cameron(a)huawei.com> This currently very much a PoC. Currently the SPDM library only provides a single function to allow a challenge / authentication of the PCI EP. SPDM exchanges must occur in one of a small set of valid squences over which the message digest used in authentication is built up. Placing that complexity in the SPDM library seems like a good way to enforce that logic, without having to do it for each transport. Signed-off-by: Jonathan Cameron <Jonathan.Cameron(a)huawei.com> --- drivers/pci/Kconfig | 9 ++++ drivers/pci/Makefile | 2 + drivers/pci/cma.c | 105 ++++++++++++++++++++++++++++++++++++++++ include/linux/pci-cma.h | 19 ++++++++ 4 files changed, 135 insertions(+) diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 8de51b64067c..407505e5c972 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -128,6 +128,15 @@ config PCI_DOE_DRIVER number of different protocols. DOE is defined in the Data Object Exchange ECN to the PCIe r5.0 spec. +config PCI_CMA + tristate "PCI Component Measurement and Authentication" + select PCI_DOE + select ASN1_ENCODER + select SPDM + help + This enables library support for the PCI Component Measurement and + Authentication ECN. This uses DMTF SPDM 1.1 + config PCI_ATS bool diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index afd9d7bd2b82..122e648d9415 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -29,9 +29,11 @@ obj-$(CONFIG_PCI_PF_STUB) += pci-pf-stub.o obj-$(CONFIG_PCI_ECAM) += ecam.o obj-$(CONFIG_PCI_P2PDMA) += p2pdma.o obj-$(CONFIG_PCI_DOE_DRIVER) += pci-doe.o +obj-$(CONFIG_PCI_CMA) += pci-cma.o obj-$(CONFIG_XEN_PCIDEV_FRONTEND) += xen-pcifront.o pci-doe-y := doe.o +pci-cma-y := cma.o # Endpoint library must be initialized before its users obj-$(CONFIG_PCI_ENDPOINT) += endpoint/ diff --git a/drivers/pci/cma.c b/drivers/pci/cma.c new file mode 100644 index 000000000000..7a14a3365300 --- /dev/null +++ b/drivers/pci/cma.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Component Measurement and Authentication was added as an ECN to the + * PCIe r5.0 spec. + * + * Copyright (C) 2021 Huawei + * Jonathan Cameron <Jonathan.Cameron(a)huawei.com> + */ + +#include <linux/module.h> +#include <linux/pci.h> +#include <linux/pci-cma.h> +#include <linux/pci-doe.h> +#include <linux/spdm.h> + +#define PCI_DOE_PROTOCOL_CMA 1 +/* Keyring that userspace can poke certs into */ +static struct key *cma_keyring; + +static int cma_spdm_ex(void *priv, struct spdm_exchange *spdm_ex) +{ + size_t request_padded_sz, response_padded_sz; + struct pci_doe_exchange ex = { + .prot = { + .vid = PCI_VENDOR_ID_PCI_SIG, + .type = PCI_DOE_PROTOCOL_CMA, + }, + }; + struct pci_doe_dev *doe_dev = priv; + int rc; + + /* DOE requires that response and request are padded to a multiple of 4 bytes */ + request_padded_sz = ALIGN(spdm_ex->request_pl_sz, sizeof(u32)); + if (request_padded_sz != spdm_ex->request_pl_sz) { + ex.request_pl = kzalloc(request_padded_sz, GFP_KERNEL); + if (!ex.request_pl) + return -ENOMEM; + memcpy(ex.request_pl, spdm_ex->request_pl, spdm_ex->request_pl_sz); + ex.request_pl_sz = request_padded_sz; + } else { + ex.request_pl = (u32 *)spdm_ex->request_pl; + ex.request_pl_sz = spdm_ex->request_pl_sz; + } + + response_padded_sz = ALIGN(spdm_ex->response_pl_sz, sizeof(u32)); + if (response_padded_sz != spdm_ex->response_pl_sz) { + ex.response_pl = kzalloc(response_padded_sz, GFP_KERNEL); + if (!ex.response_pl) { + rc = -ENOMEM; + goto err_free_req; + } + ex.response_pl_sz = response_padded_sz; + } else { + ex.response_pl = (u32 *)spdm_ex->response_pl; + ex.response_pl_sz = spdm_ex->response_pl_sz; + } + + rc = pci_doe_exchange_sync(doe_dev, &ex); + if (rc < 0) + goto err_free_rsp; + + if (response_padded_sz != spdm_ex->response_pl_sz) + memcpy(spdm_ex->response_pl, ex.response_pl, spdm_ex->response_pl_sz); + +err_free_rsp: + if (response_padded_sz != spdm_ex->response_pl_sz) + kfree(ex.response_pl); +err_free_req: + if (request_padded_sz != spdm_ex->request_pl_sz) + kfree(ex.request_pl); + + return rc; +} + +void pci_cma_init(struct pci_doe_dev *doe_dev, struct spdm_state *spdm_state) +{ + memset(spdm_state, 0, sizeof(*spdm_state)); + spdm_state->transport_ex = cma_spdm_ex; + spdm_state->transport_priv = doe_dev; + spdm_state->dev = &doe_dev->pdev->dev; + spdm_state->root_keyring = cma_keyring; +} +EXPORT_SYMBOL_GPL(pci_cma_init); + +int pci_cma_authenticate(struct spdm_state *spdm_state) +{ + return spdm_authenticate(spdm_state); +} +EXPORT_SYMBOL_GPL(pci_cma_authenticate); + +__init static int cma_keyring_init(void) +{ + cma_keyring = keyring_alloc("_cma", + KUIDT_INIT(0), KGIDT_INIT(0), + current_cred(), + (KEY_POS_ALL & ~KEY_POS_SETATTR) | + KEY_USR_VIEW | KEY_USR_READ | KEY_USR_WRITE | KEY_USR_SEARCH, + KEY_ALLOC_NOT_IN_QUOTA | KEY_ALLOC_SET_KEEP, NULL, NULL); + if (IS_ERR(cma_keyring)) + pr_err("Could not allocate cma keyring\n"); + + return 0; +} +device_initcall(cma_keyring_init); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/pci-cma.h b/include/linux/pci-cma.h new file mode 100644 index 000000000000..3790e532cd38 --- /dev/null +++ b/include/linux/pci-cma.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Component Measurement and Authentication was added as an ECN to the + * PCIe r5.0 spec. + * + * Copyright (C) 2021 Huawei + * Jonathan Cameron <Jonathan.Cameron(a)huawei.com> + */ + +#ifndef _PCI_CMA_H_ +#define _PCI_CMA_H_ +struct pci_doe_dev; +struct spdm_state; + +void pci_cma_init(struct pci_doe_dev *doe_dev, struct spdm_state *spdm_state); + +int pci_cma_authenticate(struct spdm_state *spdm_state); + +#endif -- 2.32.0

3 years, 1 month

1
0
0 0

2025

2024

2023

2022

2021

2020

Linaro-open-discussions