Import the Morello dts (SoC, FVP) from the Trusted Firmware and add Panfrost GPU/DPU support.
Co-developed-by: Carsten Haitzler Carsten.Haitzler@arm.com Signed-off-by: Vincenzo Frascino vincenzo.frascino@arm.com --- arch/arm64/boot/dts/arm/Makefile | 1 + arch/arm64/boot/dts/arm/morello-fvp.dts | 171 +++++++++++++++ arch/arm64/boot/dts/arm/morello-soc.dts | 278 ++++++++++++++++++++++++ arch/arm64/boot/dts/arm/morello.dtsi | 124 +++++++++++ 4 files changed, 574 insertions(+) create mode 100644 arch/arm64/boot/dts/arm/morello-fvp.dts create mode 100644 arch/arm64/boot/dts/arm/morello-soc.dts create mode 100644 arch/arm64/boot/dts/arm/morello.dtsi
diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile index 4382b73baef5..ed025c949e2d 100644 --- a/arch/arm64/boot/dts/arm/Makefile +++ b/arch/arm64/boot/dts/arm/Makefile @@ -6,3 +6,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb juno-scmi.dtb ju dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb +dtb-$(CONFIG_ARM64_MORELLO) += morello-soc.dtb morello-fvp.dtb diff --git a/arch/arm64/boot/dts/arm/morello-fvp.dts b/arch/arm64/boot/dts/arm/morello-fvp.dts new file mode 100644 index 000000000000..de78bcc89b55 --- /dev/null +++ b/arch/arm64/boot/dts/arm/morello-fvp.dts @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (c) 2020, Arm Limited. All rights reserved. + */ + +/dts-v1/; +#include "morello.dtsi" + +/ { + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure-firmware@ff000000 { + reg = <0 0xff000000 0 0x01000000>; + no-map; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + }; + cluster1 { + core0 { + cpu = <&CPU2>; + }; + core1 { + cpu = <&CPU3>; + }; + }; + }; + CPU0: cpu0@0 { + compatible = "arm,armv8"; + reg = <0x0 0x0>; + device_type = "cpu"; + enable-method = "psci"; + clocks = <&scmi_dvfs 0>; + }; + CPU1: cpu1@100 { + compatible = "arm,armv8"; + reg = <0x0 0x100>; + device_type = "cpu"; + enable-method = "psci"; + clocks = <&scmi_dvfs 0>; + }; + CPU2: cpu2@10000 { + compatible = "arm,armv8"; + reg = <0x0 0x10000>; + device_type = "cpu"; + enable-method = "psci"; + clocks = <&scmi_dvfs 1>; + }; + CPU3: cpu3@10100 { + compatible = "arm,armv8"; + reg = <0x0 0x10100>; + device_type = "cpu"; + enable-method = "psci"; + clocks = <&scmi_dvfs 1>; + }; + }; + + /* The first bank of memory, memory map is actually provided by UEFI. */ + memory@80000000 { + #address-cells = <2>; + #size-cells = <2>; + device_type = "memory"; + /* [0x80000000-0xffffffff] */ + reg = <0x00000000 0x80000000 0x0 0x80000000>; + }; + + memory@8080000000 { + #address-cells = <2>; + #size-cells = <2>; + device_type = "memory"; + /* [0x8080000000-0x83ffffffff] */ + reg = <0x00000080 0x80000000 0x1 0x80000000>; + }; + + virtio_block@1c170000 { + compatible = "virtio,mmio"; + reg = <0x0 0x1c170000 0x0 0x200>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + }; + + virtio_net@1c180000 { + compatible = "virtio,mmio"; + reg = <0x0 0x1c180000 0x0 0x200>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + }; + + virtio_rng@1c190000 { + compatible = "virtio,mmio"; + reg = <0x0 0x1c190000 0x0 0x200>; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + }; + + virtio_p9@1c1a0000 { + compatible = "virtio,mmio"; + reg = <0x0 0x1c1a0000 0x0 0x200>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + }; + + ethernet@1d100000 { + compatible = "smsc,lan91c111"; + reg = <0x0 0x1d100000 0x0 0x10000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + }; + + kmi@1c150000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x0 0x1c150000 0x0 0x1000>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + kmi@1c160000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x0 0x1c160000 0x0 0x1000>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + firmware { + scmi { + compatible = "arm,scmi"; + mbox-names = "tx", "rx"; + mboxes = <&mailbox 1 0 &mailbox 1 1>; + shmem = <&cpu_scp_hpri0 &cpu_scp_hpri1>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_dvfs: protocol@13 { + reg = <0x13>; + #clock-cells = <1>; + }; + }; + }; + + bp_clock24mhz: clock24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "bp:clock24mhz"; + }; +}; + +&gic { + reg = <0x0 0x30000000 0 0x10000>, /* GICD */ + <0x0 0x300c0000 0 0x80000>; /* GICR */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; +}; + + diff --git a/arch/arm64/boot/dts/arm/morello-soc.dts b/arch/arm64/boot/dts/arm/morello-soc.dts new file mode 100644 index 000000000000..f9e062331033 --- /dev/null +++ b/arch/arm64/boot/dts/arm/morello-soc.dts @@ -0,0 +1,278 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + */ + +/dts-v1/; +#include "morello.dtsi" + +/ { + + chosen { + stdout-path = "soc_uart0:115200n8"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure-firmware@ff000000 { + reg = <0 0xff000000 0 0x01000000>; + no-map; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + cpu0@0 { + compatible = "arm,armv8"; + reg = <0x0 0x0>; + device_type = "cpu"; + enable-method = "psci"; + clocks = <&scmi_dvfs 0>; + }; + cpu1@100 { + compatible = "arm,armv8"; + reg = <0x0 0x100>; + device_type = "cpu"; + enable-method = "psci"; + clocks = <&scmi_dvfs 0>; + }; + cpu2@10000 { + compatible = "arm,armv8"; + reg = <0x0 0x10000>; + device_type = "cpu"; + enable-method = "psci"; + clocks = <&scmi_dvfs 1>; + }; + cpu3@10100 { + compatible = "arm,armv8"; + reg = <0x0 0x10100>; + device_type = "cpu"; + enable-method = "psci"; + clocks = <&scmi_dvfs 1>; + }; + }; + + /* The first bank of memory, memory map is actually provided by UEFI. */ + memory@80000000 { + #address-cells = <2>; + #size-cells = <2>; + device_type = "memory"; + /* [0x80000000-0xffffffff] */ + reg = <0x00000000 0x80000000 0x0 0x7F000000>; + }; + + memory@8080000000 { + #address-cells = <2>; + #size-cells = <2>; + device_type = "memory"; + /* [0x8080000000-0x83f7ffffff] */ + reg = <0x00000080 0x80000000 0x3 0x78000000>; + }; + + smmu_pcie: iommu@4f400000 { + compatible = "arm,smmu-v3"; + reg = <0 0x4f400000 0 0x40000>; + interrupts = <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 237 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eventq", "priq", "cmdq-sync", "gerror"; + msi-parent = <&its2 0>; + #iommu-cells = <1>; + dma-coherent; + }; + + pcie_ctlr: pcie@28c0000000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + reg = <0x28 0xC0000000 0 0x10000000>; + bus-range = <0 255>; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + dma-coherent; + ranges = <0x01000000 0x00 0x00000000 0x00 0x6F000000 0x00 0x00800000>, + <0x02000000 0x00 0x60000000 0x00 0x60000000 0x00 0x0F000000>, + <0x42000000 0x09 0x00000000 0x09 0x00000000 0x1F 0xC0000000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 0 170 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 0 171 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 0 172 IRQ_TYPE_LEVEL_HIGH>; + msi-map = <0 &its_pcie 0 0x10000>; + iommu-map = <0 &smmu_pcie 0 0x10000>; + status = "okay"; + }; + + smmu_ccix: iommu@4f000000 { + compatible = "arm,smmu-v3"; + reg = <0 0x4f000000 0 0x40000>; + interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eventq", "priq", "cmdq-sync", "gerror"; + msi-parent = <&its1 0>; + #iommu-cells = <1>; + dma-coherent; + }; + + ccix_pcie_ctlr: pcie@4fc0000000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + reg = <0x4F 0xC0000000 0 0x10000000>; + bus-range = <0 255>; + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + dma-coherent; + ranges = <0x01000000 0x00 0x00000000 0x00 0x7F000000 0x00 0x00800000>, + <0x02000000 0x00 0x70000000 0x00 0x70000000 0x00 0x0F000000>, + <0x42000000 0x30 0x00000000 0x30 0x00000000 0x1F 0xC0000000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic 0 0 0 201 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 0 202 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 0 203 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 0 204 IRQ_TYPE_LEVEL_HIGH>; + msi-map = <0 &its_ccix 0 0x10000>; + iommu-map = <0 &smmu_ccix 0 0x10000>; + status = "okay"; + }; + + smmu_dp: iommu@2ce00000 { + compatible = "arm,smmu-v3"; + reg = <0 0x2ce00000 0 0x40000>; + interrupts = <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eventq", "cmdq-sync", "gerror"; + #iommu-cells = <1>; + }; + + dp0: display@2cc00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "arm,mali-d32"; + reg = <0 0x2cc00000 0 0x20000>; + interrupts = <0 69 4>; + interrupt-names = "DPU"; + clocks = <&dpu_aclk>; + clock-names = "aclk"; + iommus = <&smmu_dp 0>, <&smmu_dp 1>, <&smmu_dp 2>, <&smmu_dp 3>, + <&smmu_dp 8>; + + pl0: pipeline@0 { + reg = <0>; + clocks = <&dpu_pixel_clk>; + clock-names = "pxclk"; + pl_id = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + dp_pl0_out0: endpoint { + remote-endpoint = <&tda998x_0_input>; + }; + }; + }; + }; + }; + + i2c@1c0f0000 { + compatible = "cdns,i2c-r1p14"; + reg = <0x0 0x1c0f0000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + i2c-sda-hold-time-ns = <500>; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&dpu_aclk>; + + hdmi-transmitter@70 { + compatible = "nxp,tda998x"; + reg = <0x70>; + video-ports = <0x234501>; + port { + tda998x_0_input: endpoint { + remote-endpoint = <&dp_pl0_out0>; + }; + }; + }; + }; + + dpu_aclk: dpu_aclk { + /* 77.1 MHz derived from 24 MHz reference clock */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <350000000>; + clock-output-names = "aclk"; + }; + + dpu_pixel_clk: dpu-pixel-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <148500000>; + clock-output-names = "pxclk"; + }; + + firmware { + scmi { + compatible = "arm,scmi"; + mbox-names = "tx", "rx"; + mboxes = <&mailbox 1 0 &mailbox 1 1>; + shmem = <&cpu_scp_hpri0 &cpu_scp_hpri1>; + #address-cells = <1>; + #size-cells = <0>; + scmi_dvfs: protocol@13 { + reg = <0x13>; + #clock-cells = <1>; + }; + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + }; + }; +}; + +&gic { + reg = <0x0 0x30000000 0 0x10000>, /* GICD */ + <0x0 0x300c0000 0 0x80000>; /* GICR */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + + its1: its@30040000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x0 0x30040000 0x0 0x20000>; + }; + + its2: its@30060000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x0 0x30060000 0x0 0x20000>; + }; + + its_ccix: its@30080000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x0 0x30080000 0x0 0x20000>; + }; + + its_pcie: its@300a0000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x0 0x300a0000 0x0 0x20000>; + }; +}; + diff --git a/arch/arm64/boot/dts/arm/morello.dtsi b/arch/arm64/boot/dts/arm/morello.dtsi new file mode 100644 index 000000000000..198201fdfc71 --- /dev/null +++ b/arch/arm64/boot/dts/arm/morello.dtsi @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (c) 2020-2021, Arm Limited. All rights reserved. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "arm,morello"; + + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &soc_uart0; + }; + + gic: interrupt-controller@2c010000 { + compatible = "arm,gic-600", "arm,gic-v3"; + #address-cells = <2>; + #interrupt-cells = <3>; + #size-cells = <2>; + ranges; + interrupt-controller; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + spe-pmu { + compatible = "arm,statistical-profiling-extension-v1"; + interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; + + mailbox: mhu@45000000 { + compatible = "arm,mhu-doorbell", "arm,primecell"; + reg = <0x0 0x45000000 0x0 0x1000>; + interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mhu_lpri_rx", + "mhu_hpri_rx"; + #mbox-cells = <2>; + mbox-name = "ARM-MHU"; + clocks = <&soc_refclk50mhz>; + clock-names = "apb_pclk"; + }; + + sram: sram@45200000 { + compatible = "mmio-sram"; + reg = <0x0 0x06000000 0x0 0x8000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x06000000 0x8000>; + + cpu_scp_hpri0: scp-shmem@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x80>; + }; + + cpu_scp_hpri1: scp-shmem@80 { + compatible = "arm,scmi-shmem"; + reg = <0x80 0x80>; + }; + }; + + soc_refclk50mhz: refclk50mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "apb_pclk"; + }; + + soc_uartclk: uartclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "uartclk"; + }; + + soc_uart0: uart@2a400000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x2a400000 0x0 0x1000>; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&soc_uartclk>, <&soc_refclk50mhz>; + clock-names = "uartclk", "apb_pclk"; + status = "okay"; + }; + + gpu: gpu@2d000000 { + compatible = "arm,mali-bifrost"; + reg = <0x0 0x2d000000 0x0 0x4000>; + interrupts = <0 66 4>, <0 67 4>, <0 65 4>; + interrupt-names = "job", "mmu", "gpu"; + clocks = <&clk_mali>; + clock-names = "clk_mali"; + status = "okay"; + }; + + clk_mali: clkmali650mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <650000000>; + clock-output-names = "clk_mali"; + }; + +}; +