On Fri, Mar 01, 2024 at 11:15:57AM +0100, Kevin Brodsky wrote:
On 26/02/2024 09:20, Beata Michalska wrote:
Add capability-aware assembly macors generating full-syntax MRS/MSR
s/macors/macros/
instructions for capability system registers.
Signed-off-by: Beata Michalska beata.michalska@arm.com
arch/arm64/include/asm/sysreg.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 9988e289ce20..e2109e2c0bef 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -1071,28 +1071,56 @@ __emit_inst(0xd5200000|(\sreg)|(.L__gpr_num_\rt)) \ " .endm\n" +#define DEFINE_MRS_S_C \
- __DEFINE_ASM_GPR_NUMS \
+" .macro mrs_s_c, rt, sreg\n" \
- __emit_inst(0xC2900000|(\sreg)|(.L__gpr_num_\rt)) \
Nit: hex is normally lowercase (same below).
+" .endm\n"
#define DEFINE_MSR_S \ __DEFINE_ASM_GPR_NUMS \ " .macro msr_s, sreg, rt\n" \ __emit_inst(0xd5000000|(\sreg)|(.L__gpr_num_\rt)) \ " .endm\n" +#define DEFINE_MSR_S_C \
- __DEFINE_ASM_GPR_NUMS \
+" .macro msr_s_c, sreg, rt\n" \
- __emit_inst(0xC2800000|(\sreg)&~0x100000|(.L__gpr_num_\rt)) \
I think I understand the need for masking bit 20 in sreg (unlike similar instructions, bit 20 is 0 in capability MSR), but a comment wouldn't hurt.
Will do.
--- BR Beata
Kevin
+" .endm\n"
#define UNDEFINE_MRS_S \ " .purgem mrs_s\n" +#define UNDEFINE_MRS_S_C \ +" .purgem mrs_s_c\n"
#define UNDEFINE_MSR_S \ " .purgem msr_s\n" +#define UNDEFINE_MSR_S_C \ +" .purgem msr_s_c\n"
#define __mrs_s(v, r) \ DEFINE_MRS_S \ " mrs_s " v ", " __stringify(r) "\n" \ UNDEFINE_MRS_S +#define __mrs_s_c(v, r) \
- DEFINE_MRS_S_C \
+" mrs_s_c " v ", " __stringify(r) "\n" \
- UNDEFINE_MRS_S_C
#define __msr_s(r, v) \ DEFINE_MSR_S \ " msr_s " __stringify(r) ", " v "\n" \ UNDEFINE_MSR_S +#define __msr_s_c(r, v) \
- DEFINE_MSR_S_C \
+" msr_s_c " __stringify(r) ", " v "\n" \
- UNDEFINE_MSR_S_C
/*
- Unlike read_cpuid, calls to read_sysreg are never expected to be
- optimized away or replaced with synthetic values.