Morello Clang used to support specifying capability variables in inline assembly only via the "C" constraint. As of the latest release (1.7), standard constraints ("r", "Q") are also supported, like in Morello GCC.
We can therefore simplify various pieces of inline assembly by restoring the original constraints and getting rid of the ABI-specific macros. Inline assembly that always operates on capabilities is left unchanged, as the "C" constraint remains supported and it is more explicit (only a capability may be provided in that case).
This commit partially reverts a number of uaccess-related commits, as well as a vDSO-related commit.
Signed-off-by: Kevin Brodsky kevin.brodsky@arm.com --- arch/arm64/include/asm/futex.h | 23 +++++++++------------- arch/arm64/include/asm/uaccess.h | 14 ++++--------- arch/arm64/include/asm/vdso/gettimeofday.h | 15 ++++---------- 3 files changed, 17 insertions(+), 35 deletions(-)
diff --git a/arch/arm64/include/asm/futex.h b/arch/arm64/include/asm/futex.h index c128e4c2886e..e00f550259d3 100644 --- a/arch/arm64/include/asm/futex.h +++ b/arch/arm64/include/asm/futex.h @@ -19,10 +19,10 @@ do { \ uaccess_enable_privileged(); \ asm volatile( \ __ASM_UACCESS_BEFORE \ -" prfm pstl1strm, [%2]\n" \ -"1: ldxr %w1, [%2]\n" \ +" prfm pstl1strm, %2\n" \ +"1: ldxr %w1, %2\n" \ insn "\n" \ -"2: stlxr %w0, %w3, [%2]\n" \ +"2: stlxr %w0, %w3, %2\n" \ " cbz %w0, 3f\n" \ " sub %w4, %w4, %w0\n" \ " cbnz %w4, 1b\n" \ @@ -32,10 +32,8 @@ do { \ __ASM_UACCESS_AFTER \ _ASM_EXTABLE_UACCESS_ERR(1b, 3b, %w0) \ _ASM_EXTABLE_UACCESS_ERR(2b, 3b, %w0) \ - /* TODO [PCuABI]: temporary solution for uaddr. Should be reverted to +Q - * once LLVM supports it for capabilities. */ \ - : "=&r" (ret), "=&r" (oldval), __ASM_RW_UPTR_CONSTR (uaddr), \ - "=&r" (tmp), "+r" (loops) \ + : "=&r" (ret), "=&r" (oldval), "+Q" (*uaddr), "=&r" (tmp), \ + "+r" (loops) \ : "r" (oparg), "Ir" (-EAGAIN) \ : "memory"); \ uaccess_disable_privileged(); \ @@ -97,11 +95,11 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *_uaddr, uaccess_enable_privileged(); asm volatile("// futex_atomic_cmpxchg_inatomic\n" __ASM_UACCESS_BEFORE -" prfm pstl1strm, [%2]\n" -"1: ldxr %w1, [%2]\n" +" prfm pstl1strm, %2\n" +"1: ldxr %w1, %2\n" " sub %w3, %w1, %w5\n" " cbnz %w3, 4f\n" -"2: stlxr %w3, %w6, [%2]\n" +"2: stlxr %w3, %w6, %2\n" " cbz %w3, 3f\n" " sub %w4, %w4, %w3\n" " cbnz %w4, 1b\n" @@ -112,10 +110,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *_uaddr, __ASM_UACCESS_AFTER _ASM_EXTABLE_UACCESS_ERR(1b, 4b, %w0) _ASM_EXTABLE_UACCESS_ERR(2b, 4b, %w0) - /* TODO [PCuABI]: temporary solution for uaddr. Should be reverted to +Q once - * LLVM supports it for capabilities. */ - : "+r" (ret), "=&r" (val), __ASM_RW_UPTR_CONSTR (uaddr), "=&r" (tmp), - "+r" (loops) + : "+r" (ret), "=&r" (val), "+Q" (*uaddr), "=&r" (tmp), "+r" (loops) : "r" (oldval), "r" (newval), "Ir" (-EAGAIN) : "memory"); uaccess_disable_privileged(); diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h index 5dcff4239098..e096ea2dbf8c 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -32,21 +32,15 @@ ".arch morello+c64\n" #define __ASM_SWITCH_TO_A64 " bx #4\n" \ ".arch morello\n" -#define __ASM_RO_UPTR_CONSTR "C" -#define __ASM_RW_UPTR_CONSTR "+C" #else #define __ASM_SWITCH_TO_C64 #define __ASM_SWITCH_TO_A64 -#define __ASM_RO_UPTR_CONSTR "r" -#define __ASM_RW_UPTR_CONSTR "+r" #endif
#define __ASM_UACCESS_BEFORE __ASM_SWITCH_TO_C64 #define __ASM_UACCESS_AFTER __ASM_SWITCH_TO_A64 #define __ASM_KACCESS_BEFORE #define __ASM_KACCESS_AFTER -#define __ASM_RO_KPTR_CONSTR "r" -#define __ASM_RW_KPTR_CONSTR "+r"
static inline int __access_ok(const void __user *ptr, unsigned long size);
@@ -227,7 +221,7 @@ static inline void __user *__uaccess_mask_ptr(const void __user *ptr) __ASM_##type##ACCESS_AFTER \ _ASM_EXTABLE_##type##ACCESS_ERR_ZERO(1b, 2b, %w0, %w1) \ : "+r" (err), "=r" (x) \ - : __ASM_RO_##type##PTR_CONSTR (addr)) + : "r" (addr))
#define __raw_get_mem(ldr, x, ptr, err, type) \ do { \ @@ -318,7 +312,7 @@ do { \ __ASM_##type##ACCESS_AFTER \ _ASM_EXTABLE_##type##ACCESS_ERR(1b, 2b, %w0) \ : "+r" (err) \ - : "rZ" (x), __ASM_RO_##type##PTR_CONSTR (addr)) + : "rZ" (x), "r" (addr))
#define __raw_put_mem(str, x, ptr, err, type) \ do { \ @@ -464,7 +458,7 @@ do { \ __ASM_UACCESS_AFTER \ _ASM_EXTABLE_UACCESS_ERR_ZERO(1b, 2b, %w0, %w1) \ : "+r" (err), "=C" (x) \ - : __ASM_RO_UPTR_CONSTR (ptr)); \ + : "r" (ptr)); \ uaccess_ttbr0_disable(); \ } while (0)
@@ -501,7 +495,7 @@ do { \ __ASM_UACCESS_AFTER \ _ASM_EXTABLE_UACCESS_ERR(1b, 2b, %w0) \ : "+r" (err) \ - : "CZ" (x), __ASM_RO_UPTR_CONSTR (ptr)); \ + : "CZ" (x), "r" (ptr)); \ uaccess_ttbr0_disable(); \ } while (0)
diff --git a/arch/arm64/include/asm/vdso/gettimeofday.h b/arch/arm64/include/asm/vdso/gettimeofday.h index 17151df887d4..d0eee76d2709 100644 --- a/arch/arm64/include/asm/vdso/gettimeofday.h +++ b/arch/arm64/include/asm/vdso/gettimeofday.h @@ -15,18 +15,11 @@
#define VDSO_HAS_CLOCK_GETRES 1
-/* - * Inline Assembly Macros for Purecap - * PTR_REG(n) will expand to "cn" under purecap, and "xn" under non-purecap - * PTR_REG_OP will expand to "C" under purecap and "r" under non-purecap. - */ #if defined(__CHERI_PURE_CAPABILITY__) #define PTR_REG(n) "c" __stringify(n) -#define PTR_REG_OP "C" #else #define PTR_REG(n) "x" __stringify(n) -#define PTR_REG_OP "r" -#endif /* __CHERI_PURE_CAPABILITY__ */ +#endif
static __always_inline int gettimeofday_fallback(struct __kernel_old_timeval *_tv, @@ -40,7 +33,7 @@ int gettimeofday_fallback(struct __kernel_old_timeval *_tv, asm volatile( " svc #0\n" : "=r" (ret) - : PTR_REG_OP (tv), PTR_REG_OP (tz), "r" (nr) + : "r" (tv), "r" (tz), "r" (nr) : "memory");
return ret; @@ -57,7 +50,7 @@ long clock_gettime_fallback(clockid_t _clkid, struct __kernel_timespec *_ts) asm volatile( " svc #0\n" : "=r" (ret) - : "r" (clkid), PTR_REG_OP (ts), "r" (nr) + : "r" (clkid), "r" (ts), "r" (nr) : "memory");
return ret; @@ -74,7 +67,7 @@ int clock_getres_fallback(clockid_t _clkid, struct __kernel_timespec *_ts) asm volatile( " svc #0\n" : "=r" (ret) - : "r" (clkid), PTR_REG_OP (ts), "r" (nr) + : "r" (clkid), "r" (ts), "r" (nr) : "memory");
return ret;