On 26/02/2024 09:20, Beata Michalska wrote:
With the FEAT_HPDS2 being implemented, PBHA bits of the translation table last-level descriptors can be leveraged for implementation defined hardware use. Fields HWU61,HWU60 & HWU59 are being used by Morello to control capability loads & stores from memory (with correspondign bits
Nit: s/correspondign/corresponding/
enabled in TCR_EL2 for stage 1 and VTCR_EL2 for stage 2 for EL2 translation regime). Add their respective filed descriptors, with HWU62 being provided
s/filed/field/
for completenes only.
s/completenes/completeness/
Kevin
Signed-off-by: Beata Michalska beata.michalska@arm.com
arch/arm64/include/asm/kvm_arm.h | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h index d1fbf885283f..e80e1b7a91e0 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -109,6 +109,11 @@ /* TCR_EL2 Registers bits */ #define TCR_EL2_RES1 ((1U << 31) | (1 << 23)) +#define TCR_EL2_HWU62 (1 << 28) +#define TCR_EL2_HWU61 (1 << 27) +#define TCR_EL2_HWU60 (1 << 26) +#define TCR_EL2_HWU59 (1 << 25) +#define TCR_EL2_HPD (1 << 24) #define TCR_EL2_TBI (1 << 20) #define TCR_EL2_PS_SHIFT 16 #define TCR_EL2_PS_MASK (7 << TCR_EL2_PS_SHIFT) @@ -123,6 +128,10 @@ /* VTCR_EL2 Registers bits */ #define VTCR_EL2_RES1 (1U << 31) +#define VTCR_EL2_HWU62 TCR_EL2_HWU62 +#define VTCR_EL2_HWU61 TCR_EL2_HWU61 +#define VTCR_EL2_HWU60 TCR_EL2_HWU60 +#define VTCR_EL2_HWU59 TCR_EL2_HWU59 #define VTCR_EL2_HD (1 << 22) #define VTCR_EL2_HA (1 << 21) #define VTCR_EL2_PS_SHIFT TCR_EL2_PS_SHIFT