On 10/04/2024 21:32, Beata Michalska wrote:
On Fri, Mar 01, 2024 at 11:27:26AM +0100, Kevin Brodsky wrote:
On 26/02/2024 10:20, Beata Michalska wrote:
Disable trapping of Morello instructions on context switch.
Signed-off-by: Beata Michalska beata.michalska@arm.com
arch/arm64/include/asm/kvm_emulate.h | 5 +++++ arch/arm64/kvm/hyp/nvhe/switch.c | 5 +++++ arch/arm64/kvm/hyp/vhe/switch.c | 7 +++++++ 3 files changed, 17 insertions(+)
diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h index 78a550537b67..6ce5d7c96cad 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -587,6 +587,9 @@ static __always_inline u64 kvm_get_reset_cptr_el2(struct kvm_vcpu *vcpu) CPACR_EL1_ZEN_EL1EN); if (cpus_have_final_cap(ARM64_SME)) val |= CPACR_EL1_SMEN_EL1EN;
if (IS_ENABLED(CONFIG_ARM64_MORELLO))val |= CPACR_EL1_CEN;- } else if (has_hvhe()) { val = (CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN);
@@ -603,6 +606,8 @@ static __always_inline u64 kvm_get_reset_cptr_el2(struct kvm_vcpu *vcpu) val |= CPTR_EL2_TZ; if (cpus_have_final_cap(ARM64_SME)) val &= ~CPTR_EL2_TSM;
if (IS_ENABLED(CONFIG_ARM64_MORELLO))val &= ~CPTR_EL2_TC;return val; diff --git a/arch/arm64/kvm/hyp/nvhe/switch.c b/arch/arm64/kvm/hyp/nvhe/switch.c index e19243367408..7c4363b0691b 100644 --- a/arch/arm64/kvm/hyp/nvhe/switch.c +++ b/arch/arm64/kvm/hyp/nvhe/switch.c @@ -63,7 +63,12 @@ static void __activate_traps(struct kvm_vcpu *vcpu) __activate_traps_fpsimd32(vcpu); }
- /* Disable trapping of Morello instructions */
- if (IS_ENABLED(CONFIG_ARM64_MORELLO))
val &= ~CPTR_EL2_TC;- kvm_write_cptr_el2(val);
It doesn't look like this automatically does an ISB. Considering that it is immediately followed by Morello instructions, that could be an issue. Unless CPTR_EL2.TC already happens to be cleared, considering its initialisation in init_kernel_el?
It is indeed already cleared so what it does it makes sure that between the switches we will not lose that setting. I should probably add a comment why barrier is not needed in this case.
I'm not sure I understand the rationale in that case. If we assume it's already cleared (thus skipping the ISB), because we initialise it appropriately and never change the value in CPTR_EL2, then this addition is unnecessary.
Kevin