Unfortunately writing a test for many of these changes was difficult since we needed to check that thing A pointed to place B or that thing A had a length that spanned places B and C. Hence quite a few of the added testcases check for literal values.
These are problematic for a few different reasons, both that they may not work with different configurations and because unrelated updates need to update the tests.
We need to figure out a better way to test this. We believe the testsuite doesn't have facilities for checking this. For now we're leaving making the tests robust for later.
Here we add all the tests which the recent patch series changes and include updates to the existing tests.
Updated existing tests:
emit-relocs-morello-2.d needed updating since the new alignment meant the relocation fragment pointed to a different place. emit-relocs-morello-7.d Needed updating because we added some padding, and re-laid the sections. This just ended up with a layout with the .text section at a different location and with a different range. emit-relocs-morello-8.d Just needed updating because the extra padding moved the .data.rel.ro section a bit. The position of the relocation was not part of the test so we replaced that with an "any number" regex. emit-morello-reloc-markers-{2,3}.d Needed updating because the PCC bounds required extra alignment and that was put on the first section in the PCC bounds. That happened to be the section we were looking at. morello-capinit.d Needed updating because this change actually fixed a problem with our calculation of the pcc bounds. Now we calculate the pcc_low and pcc_high *after* having made all our adjustments, the bounds we add on the capability start at the first section we want to contain. morello-stubs.d Updated just becase the location of our functions was changed due to the text section change. morello-stubs-static.d Updated because the location of the .text_low section changed along with all the code in it. Hence our stubs that needed to point to these functions also changed. c64-ifunc-{2,2-local,3a}.d Updated because the .text section moved and hence the address of the foo function we wanted to point to was adjusted. morello-sizeless-{got,global,local}-syms.d Again, .data .bss and .got sections ended up moved so addresses of the capabilities we wanted to point at all changed.
############### Attachment also inlined for ease of reply ###############
diff --git a/ld/testsuite/ld-aarch64/aarch64-elf.exp b/ld/testsuite/ld-aarch64/aarch64-elf.exp index 01f65dc934de3f012b6e134ff2ccebd1f4207650..837b9df877276029cf8d036d75de02f70e224bc0 100644 --- a/ld/testsuite/ld-aarch64/aarch64-elf.exp +++ b/ld/testsuite/ld-aarch64/aarch64-elf.exp @@ -262,6 +262,12 @@ run_dump_test_lp64 "morello-capinit" run_dump_test_lp64 "morello-stubs" run_dump_test_lp64 "morello-stubs-static" run_dump_test_lp64 "morello-sec-round" +run_dump_test_lp64 "morello-sec-round-adjust" +run_dump_test_lp64 "morello-sec-always-align" +run_dump_test_lp64 "morello-sec-round-pcc-needed" +run_dump_test_lp64 "morello-sec-round-data-only" +run_dump_test_lp64 "morello-sec-round-include-relro" +run_dump_test_lp64 "morello-pcc-bounds-include-readonly" run_dump_test_lp64 "morello-tlsdesc" run_dump_test_lp64 "morello-tlsdesc-static" run_dump_test_lp64 "morello-tlsdesc-staticpie" diff --git a/ld/testsuite/ld-aarch64/c64-ifunc-2-local.d b/ld/testsuite/ld-aarch64/c64-ifunc-2-local.d index 8c7fe038cd5b09eee772fbb00a7fe620cfcaef59..c85443fe71acb15f04d749cbb159fc002893d46c 100644 --- a/ld/testsuite/ld-aarch64/c64-ifunc-2-local.d +++ b/ld/testsuite/ld-aarch64/c64-ifunc-2-local.d @@ -5,9 +5,9 @@ #source: ifunc-2-local.s
#... -0+(110|180|1a0) <__GI_foo>: +0+(110|180|1a0|1b8) <__GI_foo>: #... -[ \t0-9a-f]+:[ \t0-9a-f]+bl[ \t0-9a-f]+<*ABS*+0x(110|180|1a0)@plt> +[ \t0-9a-f]+:[ \t0-9a-f]+bl[ \t0-9a-f]+<*ABS*+0x(110|180|1a0|1b8)@plt> [ \t0-9a-f]+:[ \t0-9a-f]+adrp[ \t]+c0, 0 <.*> -[ \t0-9a-f]+:[ \t0-9a-f]+add[ \t]+c0, c0, #0x(101|171|191) +[ \t0-9a-f]+:[ \t0-9a-f]+add[ \t]+c0, c0, #0x(101|171|191|1a9) #pass diff --git a/ld/testsuite/ld-aarch64/c64-ifunc-2.d b/ld/testsuite/ld-aarch64/c64-ifunc-2.d index 64a8b808f91856dccf1b3ea4617b91446a8ea94b..b87908b27a4366a181ddee8b7e4b7343ebd3f4b7 100644 --- a/ld/testsuite/ld-aarch64/c64-ifunc-2.d +++ b/ld/testsuite/ld-aarch64/c64-ifunc-2.d @@ -5,9 +5,9 @@ #source: ifunc-2.s
#... -0+(130|1a0|1c8) <foo>: +0+(130|1a0|1c8|1e0) <foo>: #... -[ \t0-9a-f]+:[ \t0-9a-f]+bl[ \t0-9a-f]+<*ABS*+0x(130|1a0|1c8)@plt> +[ \t0-9a-f]+:[ \t0-9a-f]+bl[ \t0-9a-f]+<*ABS*+0x(130|1a0|1c8|1e0)@plt> [ \t0-9a-f]+:[ \t0-9a-f]+adrp[ \t]+c0, 0 <.*> -[ \t0-9a-f]+:[ \t0-9a-f]+add[ \t]+c0, c0, #0x(120|190|1b8) +[ \t0-9a-f]+:[ \t0-9a-f]+add[ \t]+c0, c0, #0x(120|190|1b8|1d0) #pass diff --git a/ld/testsuite/ld-aarch64/c64-ifunc-3a.d b/ld/testsuite/ld-aarch64/c64-ifunc-3a.d index d680cde1c762149d3cd02eb612908bb0f23d98e0..bd36b23545e800cd5d952d730ac36ad3c40d0a31 100644 --- a/ld/testsuite/ld-aarch64/c64-ifunc-3a.d +++ b/ld/testsuite/ld-aarch64/c64-ifunc-3a.d @@ -5,7 +5,7 @@ #objdump: -dw
#... -0+(150|1d0|1e8) <__GI_foo>: +0+(150|1d0|1e8|200) <__GI_foo>: #... -[ \t0-9a-f]+:[ \t0-9a-f]+bl[ \t0-9a-f]+<*ABS*+0x(150|1d0|1e8)@plt> +[ \t0-9a-f]+:[ \t0-9a-f]+bl[ \t0-9a-f]+<*ABS*+0x(150|1d0|1e8|200)@plt> #pass diff --git a/ld/testsuite/ld-aarch64/emit-morello-reloc-markers-2.d b/ld/testsuite/ld-aarch64/emit-morello-reloc-markers-2.d index c2fcd5001fb2bc99977d7407ef9ed9165f440a44..f65f859deaa51c442079a4b0b4598b499b32e4bc 100644 --- a/ld/testsuite/ld-aarch64/emit-morello-reloc-markers-2.d +++ b/ld/testsuite/ld-aarch64/emit-morello-reloc-markers-2.d @@ -12,7 +12,7 @@
Sections: Idx Name Size VMA LMA File off Algn - 0 .rela.dyn 00000030 0000000000000000 0000000000000000 00010000 2**3 + 0 .rela.dyn 00000030 0000000000000000 0000000000000000 00010000 .* CONTENTS, ALLOC, LOAD, READONLY, DATA .* .got .* .* diff --git a/ld/testsuite/ld-aarch64/emit-morello-reloc-markers-3.d b/ld/testsuite/ld-aarch64/emit-morello-reloc-markers-3.d index 8ebf8420ca354daa4166883329526ce711a3793a..ea373cd24260c330ef92e836705fafc0392fd74b 100644 --- a/ld/testsuite/ld-aarch64/emit-morello-reloc-markers-3.d +++ b/ld/testsuite/ld-aarch64/emit-morello-reloc-markers-3.d @@ -12,7 +12,7 @@
Sections: Idx Name Size VMA LMA File off Algn - 0 .rela.dyn 00000018 0000000000000000 0000000000000000 00010000 2**3 + 0 .rela.dyn 00000018 0000000000000000 0000000000000000 00010000 .* CONTENTS, ALLOC, LOAD, READONLY, DATA .* .got .* .* diff --git a/ld/testsuite/ld-aarch64/emit-relocs-morello-2.d b/ld/testsuite/ld-aarch64/emit-relocs-morello-2.d index a7077214be83beb1a099b57805498dfaa6fb263f..fe59dee85f7bbbc8a11ca36168068ae3dfbd1564 100644 --- a/ld/testsuite/ld-aarch64/emit-relocs-morello-2.d +++ b/ld/testsuite/ld-aarch64/emit-relocs-morello-2.d @@ -23,7 +23,7 @@ Disassembly of section .got:
Disassembly of section .data:
-.* <str>: +0000000000010360 <str>: .*: 6c6c6548 .* .*: 6874206f .* .*: 20657265 .* @@ -34,11 +34,11 @@ Disassembly of section .data: .*: R_AARCH64_RELATIVE *ABS*+.*
.* <ptr>: -.*: 00010350 .* +.*: 00010360 .* ...
.* <cap>: -.*: 00010350 .* +.*: 00010360 .* .*: R_MORELLO_RELATIVE *ABS* .*: 00000000 .* .*: 0000001b .* diff --git a/ld/testsuite/ld-aarch64/emit-relocs-morello-7.d b/ld/testsuite/ld-aarch64/emit-relocs-morello-7.d index bbf451ec9425df80631988aff699bc822189bbfd..c32d307eb7e05d5c5d06944f09b823246f8e9474 100644 --- a/ld/testsuite/ld-aarch64/emit-relocs-morello-7.d +++ b/ld/testsuite/ld-aarch64/emit-relocs-morello-7.d @@ -12,13 +12,13 @@ # # Point here is that the __text_start and __data_other symbols should end up # pointing into the text section, which should mean that they have PCC bounds -# and their value includes an addend. These are the symbols used in the first -# and last LDR's in the function. +# and the value of the __data_other symbol should include an addend. These are +# the symbols used in the first and last LDR's in the function. # # Meanwhile, the __text_other symbol should have bounds of everything remaining # in the section *before* it (which is nothing), and the __data_start symbol -# should have bounds spanning the entire section *after* it (which is the data -# section). +# should have bounds spanning the entire section *after* it (which happens to +# be the .interp section). # #source: emit-relocs-morello-7.s #as: -march=morello+c64 @@ -30,7 +30,7 @@
Disassembly of section .text:
-.* <obj>: +0000000000000230 <obj>: .*: c2400400 ldr c0, [c0, #16] .*: c2401000 ldr c0, [c0, #64] .*: c2400c00 ldr c0, [c0, #48] @@ -44,24 +44,24 @@ Disassembly of section .data: Disassembly of section .got:
0000000000001000 <.got>: - 1000: 00000120 .* + 1000: [0-9a-f]+ .* ... - 1010: 000001e8 .* - 1010: R_MORELLO_RELATIVE *ABS*+0x38 + 1010: 00000230 .* + 1010: R_MORELLO_RELATIVE *ABS* 1014: 00000000 .* - 1018: 00000e68 .* + 1018: 00000e20 .* 101c: 04000000 .* - 1020: 000001e8 .* - 1020: R_MORELLO_RELATIVE *ABS*+0x48 + 1020: 00000230 .* + 1020: R_MORELLO_RELATIVE *ABS*+0x10 1024: 00000000 .* - 1028: 00000e68 .* + 1028: 00000e20 .* 102c: 04000000 .* - 1030: 00000230 .* + 1030: 00000240 .* 1030: R_MORELLO_RELATIVE *ABS* 1034: 00000000 .* 1038: 0000000d .* 103c: 01000000 .* - 1040: 00000220 .* + 1040: 00000230 .* 1040: R_MORELLO_RELATIVE *ABS* ... 104c: 02000000 .* diff --git a/ld/testsuite/ld-aarch64/emit-relocs-morello-7.s b/ld/testsuite/ld-aarch64/emit-relocs-morello-7.s index 3ed82287423bb2f399db384b17277c04cf3c84a9..43104fd430b0ba7f146dd10b58f94bdca6cbe31b 100644 --- a/ld/testsuite/ld-aarch64/emit-relocs-morello-7.s +++ b/ld/testsuite/ld-aarch64/emit-relocs-morello-7.s @@ -8,7 +8,7 @@ # should get this compatibility hack (and some linker script defined symbols # that should not get the compatibility hack). .arch morello+c64 - .section othersection,"aw" + .section .othersection,"aw",@progbits .asciz "Hello there ;-)" .data .word 10 diff --git a/ld/testsuite/ld-aarch64/emit-relocs-morello-8.d b/ld/testsuite/ld-aarch64/emit-relocs-morello-8.d index e907f7de72e084263acd208374c09e91d6bd065f..3bf1e62be303d4b788ad4d1f657b4ec905a3afce 100644 --- a/ld/testsuite/ld-aarch64/emit-relocs-morello-8.d +++ b/ld/testsuite/ld-aarch64/emit-relocs-morello-8.d @@ -12,7 +12,7 @@ Disassembly of section .data.rel.ro:
0.* <.LC1>: .*: 00001000 udf #4096 - 101e0: R_MORELLO_RELATIVE *ABS* + [0-9a-f]+: R_MORELLO_RELATIVE *ABS* .*: 00000000 udf #0 .*: 00000004 udf #4 .*: 02000000 add c0, c0, #0x0 diff --git a/ld/testsuite/ld-aarch64/morello-capinit.d b/ld/testsuite/ld-aarch64/morello-capinit.d index 54b981a60b9518d9d9fcba28c38019e44828162c..0050df311ac03275d00d69bb57ad7ab48f92eeea 100644 --- a/ld/testsuite/ld-aarch64/morello-capinit.d +++ b/ld/testsuite/ld-aarch64/morello-capinit.d @@ -20,37 +20,37 @@ Disassembly of section .inspectionsection:
[0-9a-f]+ <ct_outer_start>: .*: [0-9a-f]+ .* - .*: R_MORELLO_RELATIVE *ABS*+0x[0-9a-f]+ + .*: R_MORELLO_RELATIVE *ABS* .*: 00000000 .* -.*: 00000270 .* +.*: 00000278 .* .*: 04000000 .*
[0-9a-f]+ <ct_start>: .*: [0-9a-f]+ .* - .*: R_MORELLO_RELATIVE *ABS*+0x[0-9a-f]+ + .*: R_MORELLO_RELATIVE *ABS* .*: 00000000 .* -.*: 00000270 .* +.*: 00000278 .* .*: 04000000 .*
[0-9a-f]+ <ct1_start>: .*: [0-9a-f]+ .* .*: R_MORELLO_RELATIVE *ABS*+0x[0-9a-f]+ .*: 00000000 .* -.*: 00000270 .* +.*: 00000278 .* .*: 04000000 .*
[0-9a-f]+ <ct1_end>: .*: [0-9a-f]+ .* .*: R_MORELLO_RELATIVE *ABS*+0x[0-9a-f]+ .*: 00000000 .* -.*: 00000270 .* +.*: 00000278 .* .*: 04000000 .*
[0-9a-f]+ <ct_end>: .*: [0-9a-f]+ .* .*: R_MORELLO_RELATIVE *ABS*+0x[0-9a-f]+ .*: 00000000 .* -.*: 00000270 .* +.*: 00000278 .* .*: 04000000 .*
[0-9a-f]+ <cd_outer_start>: diff --git a/ld/testsuite/ld-aarch64/morello-pcc-bounds-include-readonly.d b/ld/testsuite/ld-aarch64/morello-pcc-bounds-include-readonly.d new file mode 100644 index 0000000000000000000000000000000000000000..9c4aa81b9699a03dc4f661d86323a15532180d4f --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-pcc-bounds-include-readonly.d @@ -0,0 +1,39 @@ +# Checking that we include READONLY ALLOC sections in PCC bounds. +# +# Check is done using the fragment values to show what the size of the PCC +# bounds is given as, and we reorder sections so that the READONLY ALLOC +# section is after all executable sections and RELRO sections. +# +# Test is implemented by ensuring that .othersection is outside of RELRO and is +# the last section that should be included in PCC bounds, and that .data is +# directly after it. This is done with a linker script. If we don't +# include READONLY ALLOC sections in our PCC bounds then .othersection will not +# be within the range of the `obj` capability. +# +#source: morello-pcc-bounds-include-readonly.s +#as: -march=morello+c64 +#ld: -static -pie -T morello-pcc-bounds-include-readonly.ld +#objdump: -j .data -j .text -j .othersection -DR + +.*: file format .* + + +Disassembly of section .text: + +00000000000001a0 <obj>: +#... + +Disassembly of section .othersection: + +0000000000012000 <othersection_start>: +#... + +Disassembly of section .data: + +0000000000014000 <data_start>: + [0-9a-f]+: 000001a0 udf #416 + 14000: R_MORELLO_RELATIVE *ABS* + [0-9a-f]+: 00000000 udf #0 + [0-9a-f]+: 00011f00 .inst 0x00011f00 ; undefined + [0-9a-f]+: 04000000 add z0.b, p0/m, z0.b, z0.b + diff --git a/ld/testsuite/ld-aarch64/morello-pcc-bounds-include-readonly.ld b/ld/testsuite/ld-aarch64/morello-pcc-bounds-include-readonly.ld new file mode 100644 index 0000000000000000000000000000000000000000..53a94a79d68174163eb67314226af2e7195028da --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-pcc-bounds-include-readonly.ld @@ -0,0 +1,11 @@ +SECTIONS { + . = SEGMENT_START("text-segment", 0x1a0); + .text : { *(.text) } + . = DATA_SEGMENT_ALIGN (CONSTANT (MAXPAGESIZE), CONSTANT (COMMONPAGESIZE)); + .dynamic : { *(.dynamic) } + .got : { *(.got.plt) *(.igot.plt) *(.got) *(.igot) } + . = DATA_SEGMENT_RELRO_END (0, .); + .othersection ALIGN(0x2000) : { *(.othersection*) } + .data ALIGN(0x2000) : { *(.data) } + . = DATA_SEGMENT_END (.); +} diff --git a/ld/testsuite/ld-aarch64/morello-pcc-bounds-include-readonly.s b/ld/testsuite/ld-aarch64/morello-pcc-bounds-include-readonly.s new file mode 100644 index 0000000000000000000000000000000000000000..5727022ca9a69e97857841f32144967c16c57920 --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-pcc-bounds-include-readonly.s @@ -0,0 +1,18 @@ +.arch morello+c64 + + .section .othersection,"a",@progbits +othersection_start: + .asciz "Hello there ;-)" + + .data +data_start: + .chericap obj + .text + +obj: + + ldr c0, [c0] + ldr c0, [c0] + ldr c0, [c0] + ldr c0, [c0] + diff --git a/ld/testsuite/ld-aarch64/morello-sec-round-adjust.d b/ld/testsuite/ld-aarch64/morello-sec-round-adjust.d new file mode 100644 index 0000000000000000000000000000000000000000..f00e6a0212857a7d9159c4809aa9d68caa9bdeeb --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-sec-round-adjust.d @@ -0,0 +1,19 @@ +#as: -march=morello+c64 +#ld: -static -T morello-sec-round-adjust.ld +#objdump: -x +#... +Sections: +Idx Name Size VMA LMA File off Algn +#... + 0 .text 00000109 0000000000000200 [0-9a-f]+ [0-9a-f]+ 2**9 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .data.rel.ro 00100200 0000000000000400 0000000000000400 00000400 2**9 + CONTENTS, ALLOC, LOAD, DATA + 2 .got 00000030 0000000000100600 0000000000100600 00100600 2**4 + CONTENTS, ALLOC, LOAD, DATA + 3 .got.plt 00000030 0000000000100630 0000000000100630 00100630 2**4 + CONTENTS, ALLOC, LOAD, DATA + 4 .rela.dyn 000001a0 0000000000100660 0000000000100660 00100660 2**3 + CONTENTS, ALLOC, LOAD, READONLY, DATA +#pass + diff --git a/ld/testsuite/ld-aarch64/morello-sec-round-adjust.ld b/ld/testsuite/ld-aarch64/morello-sec-round-adjust.ld new file mode 100644 index 0000000000000000000000000000000000000000..87613d0f3b3fa1321c26160b8cf421c541ba004d --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-sec-round-adjust.ld @@ -0,0 +1,17 @@ +SECTIONS { + . = SIZEOF_HEADERS; + .text : + { + *(.text) + } + .data.rel.ro : + { + __data_rel_ro_startsym = .; + *(.data.rel.ro) + } + .got : { *(.got) } + .iplt : { *(.iplt) } + .data : { *(.data) } + .rela.dyn : { *(.rela.dyn) } + .interp : { *(.interp) } +} diff --git a/ld/testsuite/ld-aarch64/morello-sec-round-adjust.s b/ld/testsuite/ld-aarch64/morello-sec-round-adjust.s new file mode 100644 index 0000000000000000000000000000000000000000..09de3cf246a63f3e662a83b2328fcab3d27d3575 --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-sec-round-adjust.s @@ -0,0 +1,22 @@ +.text +__start: + # Use a GOT relocation because the linker currently doesn't do the + # padding and alignment unless we have GOT relocations. This is + # another linker bug that we need to fix. + adrp c0, :got:__data_rel_ro_startsym + ret +.zero 0x100 +.byte 1 +.section .data.rel.ro,"aw",@progbits +# We use a linker defined symbol that points into .data.rel.ro so that the +# linker will need to ensure this section is aligned and padded so that its +# bounds can be precisely represented by a capability. This is done in the +# linker script. +# +# Here we ensure that the size of the section is large enough that it will need +# padding. +.zero 0x100001 +.section .got,"aw",@progbits +.capinit __data_rel_ro_startsym +.xword 0 +.xword 0 diff --git a/ld/testsuite/ld-aarch64/morello-sec-round-data-only.d b/ld/testsuite/ld-aarch64/morello-sec-round-data-only.d new file mode 100644 index 0000000000000000000000000000000000000000..d3761e0eaf0175ccc9d395e064961f38589d760a --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-sec-round-data-only.d @@ -0,0 +1,15 @@ +#as: -march=morello+c64 +#ld: -static -T morello-sec-round-adjust.ld +#objdump: -x +#... +Sections: +Idx Name Size VMA LMA File off Algn +#... + 0 .text 00000101 0000000000000078 [0-9a-f]+ [0-9a-f]+ 2**0 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .data.rel.ro 00100200 [0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 2**9 + CONTENTS, ALLOC, LOAD, DATA +#... + 3 .rela.dyn 00000018 [0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 2**3 +#pass + diff --git a/ld/testsuite/ld-aarch64/morello-sec-round-data-only.ld b/ld/testsuite/ld-aarch64/morello-sec-round-data-only.ld new file mode 100644 index 0000000000000000000000000000000000000000..87613d0f3b3fa1321c26160b8cf421c541ba004d --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-sec-round-data-only.ld @@ -0,0 +1,17 @@ +SECTIONS { + . = SIZEOF_HEADERS; + .text : + { + *(.text) + } + .data.rel.ro : + { + __data_rel_ro_startsym = .; + *(.data.rel.ro) + } + .got : { *(.got) } + .iplt : { *(.iplt) } + .data : { *(.data) } + .rela.dyn : { *(.rela.dyn) } + .interp : { *(.interp) } +} diff --git a/ld/testsuite/ld-aarch64/morello-sec-round-data-only.s b/ld/testsuite/ld-aarch64/morello-sec-round-data-only.s new file mode 100644 index 0000000000000000000000000000000000000000..0082c5701638506d3dbc07dc1f7febe8052e1985 --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-sec-round-data-only.s @@ -0,0 +1,17 @@ +.text +.zero 0x100 +.byte 1 +.section .data.rel.ro,"aw",@progbits +# We use a linker defined symbol that points into .data.rel.ro so that the +# linker will need to ensure this section is aligned and padded so that its +# bounds can be precisely represented by a capability. This is done in the +# linker script. +# +# Here we ensure that the size of the section is large enough that it will need +# padding. +.zero 0x100001 +.section .got,"aw",@progbits +.capinit __data_rel_ro_startsym +.xword 0 +.xword 0 + diff --git a/ld/testsuite/ld-aarch64/morello-sec-round-include-relro.d b/ld/testsuite/ld-aarch64/morello-sec-round-include-relro.d new file mode 100644 index 0000000000000000000000000000000000000000..1848e83ec1243e4446282214e0fa51ec0adda206 --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-sec-round-include-relro.d @@ -0,0 +1,41 @@ +# Checking that we include RELRO sections in PCC bounds. +# +# Check is done using the fragment values to show what the size of the PCC +# bounds is given as, and we reorder sections so that at least one RELRO +# section is ater all READONLY ALLOC section. +# +# Test only works if we have relro, so is unsupported bare-metal. +# +# Test is implemented by ensuring that the .data.rel.ro is the last section in +# the RELRO segment, and that .data is directly after it. This is ensured with +# a linker script. If we don't include RELRO in our PCC bounds then +# .data.rel.ro will not be within the range of the `obj` capability (since the +# .data.rel.ro section itself is marked as being writeable). +# +#target: [check_relro_support] +#source: morello-sec-round-include-relro.s +#as: -march=morello+c64 +#ld: -static -pie -z relro -z now -T morello-sec-round-include-relro.ld +#objdump: -j .data -j .text -j .data.rel.ro -DR + +.*: file format .* + + +Disassembly of section .text: + +00000000000001a0 <obj>: +#... + +Disassembly of section .data.rel.ro: + +0000000000010ff0 <data_relro_start>: +#... + +Disassembly of section .data: + +0000000000011000 <data_start>: + 11000: 000001a0 udf #416 + 11000: R_MORELLO_RELATIVE *ABS* + 11004: 00000000 udf #0 + 11008: 00010e60 .inst 0x00010e60 ; undefined + 1100c: 04000000 add z0.b, p0/m, z0.b, z0.b diff --git a/ld/testsuite/ld-aarch64/morello-sec-round-include-relro.ld b/ld/testsuite/ld-aarch64/morello-sec-round-include-relro.ld new file mode 100644 index 0000000000000000000000000000000000000000..f44b5e920082a0b3601819cf7114b1a6dcee6b62 --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-sec-round-include-relro.ld @@ -0,0 +1,12 @@ +SECTIONS { + . = SEGMENT_START("text-segment", SIZEOF_HEADERS); + .text : { *(.text) } + . = DATA_SEGMENT_ALIGN (CONSTANT (MAXPAGESIZE), CONSTANT (COMMONPAGESIZE)); + .dynamic : { *(.dynamic) } + .got : { *(.got.plt) *(.igot.plt) *(.got) *(.igot) } + .data.rel.ro : { *(.data.rel.ro*) } + . = DATA_SEGMENT_RELRO_END (0, .); + .data : { *(.data) } + . = DATA_SEGMENT_END (.); +} + diff --git a/ld/testsuite/ld-aarch64/morello-sec-round-include-relro.s b/ld/testsuite/ld-aarch64/morello-sec-round-include-relro.s new file mode 100644 index 0000000000000000000000000000000000000000..afba11eb609ec43fdba637c6cd75834918cb65f7 --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-sec-round-include-relro.s @@ -0,0 +1,17 @@ +.arch morello+c64 + + .section .data.rel.ro.local,"aw",@progbits +data_relro_start: + .asciz "Hello there ;-)" + + .data +data_start: + .chericap obj + .text + +obj: + + ldr c0, [c0] + ldr c0, [c0] + ldr c0, [c0] + ldr c0, [c0] diff --git a/ld/testsuite/ld-aarch64/morello-sec-round-pcc-needed.d b/ld/testsuite/ld-aarch64/morello-sec-round-pcc-needed.d new file mode 100644 index 0000000000000000000000000000000000000000..4aebfccce9a615f204c81a09b09c75cc25355c61 --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-sec-round-pcc-needed.d @@ -0,0 +1,14 @@ +#as: -march=morello+c64 +#ld: -static +#objdump: -x +#... +Sections: +Idx Name Size VMA LMA File off Algn +#... + 0 .text 00003000 [0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .alt 00003000 [0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 2**0 + CONTENTS, ALLOC, LOAD, READONLY, CODE +#pass + + diff --git a/ld/testsuite/ld-aarch64/morello-sec-round-pcc-needed.s b/ld/testsuite/ld-aarch64/morello-sec-round-pcc-needed.s new file mode 100644 index 0000000000000000000000000000000000000000..1d616778df4e6c04d4d6157689cbe89589a0da90 --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-sec-round-pcc-needed.s @@ -0,0 +1,10 @@ +# Here we want to make sure that if we have a set of sections which do not need +# to be adjusted for morello precise bounds, but the total PCC range *does* +# need to be adjusted for Morello precise bounds then we adjust that PCC range. +.text + .global _start +_start: + ret + .zero 0x2ffc +.section .alt,"ax",@progbits + .zero 0x3000 diff --git a/ld/testsuite/ld-aarch64/morello-sec-round.d b/ld/testsuite/ld-aarch64/morello-sec-round.d index b553a604acd92a2b0c5e151546e2c19a04101f70..0b8a9b982e06f75688245917357bb5c4822bb0e1 100644 --- a/ld/testsuite/ld-aarch64/morello-sec-round.d +++ b/ld/testsuite/ld-aarch64/morello-sec-round.d @@ -5,7 +5,7 @@ Sections: Idx Name Size VMA LMA File off Algn #... - 1 .text_sec 00020004 ...........20000 [0-9a-f]+ [0-9a-f]+ 2**17 + 1 .text_sec 00020040 ...........20000 [0-9a-f]+ [0-9a-f]+ 2**17 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 ..* [0-9a-f]+ ...........40040 [0-9a-f]+ [0-9a-f]+ .* #pass diff --git a/ld/testsuite/ld-aarch64/morello-sizeless-global-syms.d b/ld/testsuite/ld-aarch64/morello-sizeless-global-syms.d index 629cc44cad520e9212ab96740d7c78fdde3063fc..89c7963b789dba65b7bb00c07c7197bb5759a8d9 100644 --- a/ld/testsuite/ld-aarch64/morello-sizeless-global-syms.d +++ b/ld/testsuite/ld-aarch64/morello-sizeless-global-syms.d @@ -9,21 +9,21 @@ Disassembly of section .data:
[0-9a-f]+ <ptr3>: - [0-9a-f]+: 00010440.* + [0-9a-f]+: 00010450.* [0-9a-f]+: R_MORELLO_RELATIVE *ABS* [0-9a-f]+: 00000000.* [0-9a-f]+: 00000000.* [0-9a-f]+: 02000000.*
[0-9a-f]+ <ptr2>: - [0-9a-f]+: 00010444.* + [0-9a-f]+: 00010454.* [0-9a-f]+: R_MORELLO_RELATIVE *ABS* [0-9a-f]+: 00000000.* [0-9a-f]+: 00000000.* [0-9a-f]+: 02000000.*
[0-9a-f]+ <ptr1>: - [0-9a-f]+: 00010448.* + [0-9a-f]+: 00010458.* [0-9a-f]+: R_MORELLO_RELATIVE *ABS* [0-9a-f]+: 00000000.* [0-9a-f]+: 00000000.* @@ -31,7 +31,7 @@ Disassembly of section .data:
Disassembly of section .bss:
-0000000000010440 <baz>: +0000000000010450 <baz>: [0-9a-f]+: 00000000.*
[0-9a-f]+ <bar>: diff --git a/ld/testsuite/ld-aarch64/morello-sizeless-got-syms.d b/ld/testsuite/ld-aarch64/morello-sizeless-got-syms.d index b28fca9f70d42fa1dea1a9ab92c57ccc324426ee..82131d11dde1995214bff673c46d925facd2650b 100644 --- a/ld/testsuite/ld-aarch64/morello-sizeless-got-syms.d +++ b/ld/testsuite/ld-aarch64/morello-sizeless-got-syms.d @@ -9,17 +9,17 @@ Disassembly of section .text:
[0-9a-f]+ <get_foo>: [0-9a-f]+: 90800080 adrp c0, 10000 .* - [0-9a-f]+: c240d800 ldr c0, [c0, #864] + [0-9a-f]+: c240dc00 ldr c0, [c0, #880] [0-9a-f]+: c2c253c0 ret c30
[0-9a-f]+ <get_bar>: [0-9a-f]+: 90800080 adrp c0, 10000 .* - [0-9a-f]+: c240dc00 ldr c0, [c0, #880] + [0-9a-f]+: c240e000 ldr c0, [c0, #896] [0-9a-f]+: c2c253c0 ret c30
[0-9a-f]+ <get_baz>: [0-9a-f]+: 90800080 adrp c0, 10000 .* - [0-9a-f]+: c240d400 ldr c0, [c0, #848] + [0-9a-f]+: c240d800 ldr c0, [c0, #864] [0-9a-f]+: c2c253c0 ret c30
[0-9a-f]+ <_start>: @@ -27,22 +27,22 @@ Disassembly of section .text:
Disassembly of section .got:
-0000000000010340 <.got>: +0000000000010350 <.got>: [0-9a-f]+: .* [0-9a-f]+: .* [0-9a-f]+: .* [0-9a-f]+: .* - [0-9a-f]+: 000103b0 .* + [0-9a-f]+: 000103c0 .* [0-9a-f]+: R_MORELLO_RELATIVE *ABS* [0-9a-f]+: 00000000 .* [0-9a-f]+: 00000000 .* [0-9a-f]+: 02000000 .* - [0-9a-f]+: 000103b8 .* + [0-9a-f]+: 000103c8 .* [0-9a-f]+: R_MORELLO_RELATIVE *ABS* [0-9a-f]+: 00000000 .* [0-9a-f]+: 00000000 .* [0-9a-f]+: 02000000 .* - [0-9a-f]+: 000103b4 .* + [0-9a-f]+: 000103c4 .* [0-9a-f]+: R_MORELLO_RELATIVE *ABS* [0-9a-f]+: 00000000 .* [0-9a-f]+: 00000000 .* @@ -50,7 +50,7 @@ Disassembly of section .got:
Disassembly of section .bss:
-00000000000103b0 <baz>: +00000000000103c0 <baz>: [0-9a-f]+: 00000000 .*
[0-9a-f]+ <bar>: diff --git a/ld/testsuite/ld-aarch64/morello-sizeless-local-syms.d b/ld/testsuite/ld-aarch64/morello-sizeless-local-syms.d index 5439d54b66c0c786087c25a6a74fb27630b8eb22..2f74b7a643ded8078e206daf81b40997705926ba 100644 --- a/ld/testsuite/ld-aarch64/morello-sizeless-local-syms.d +++ b/ld/testsuite/ld-aarch64/morello-sizeless-local-syms.d @@ -9,21 +9,21 @@ Disassembly of section .data:
[0-9a-f]+ <ptr3>: - [0-9a-f]+: 00010440.* + [0-9a-f]+: 00010450.* [0-9a-f]+: R_MORELLO_RELATIVE *ABS* [0-9a-f]+: 00000000.* [0-9a-f]+: 00000000.* [0-9a-f]+: 02000000.*
[0-9a-f]+ <ptr2>: - [0-9a-f]+: 00010444.* + [0-9a-f]+: 00010454.* [0-9a-f]+: R_MORELLO_RELATIVE *ABS* [0-9a-f]+: 00000000.* [0-9a-f]+: 00000000.* [0-9a-f]+: 02000000.*
[0-9a-f]+ <ptr1>: - [0-9a-f]+: 00010448.* + [0-9a-f]+: 00010458.* [0-9a-f]+: R_MORELLO_RELATIVE *ABS* [0-9a-f]+: 00000000.* [0-9a-f]+: 00000000.* @@ -31,7 +31,7 @@ Disassembly of section .data:
Disassembly of section .bss:
-0000000000010440 <baz>: +0000000000010450 <baz>: [0-9a-f]+: 00000000.*
[0-9a-f]+ <bar>: diff --git a/ld/testsuite/ld-aarch64/morello-stubs-static.d b/ld/testsuite/ld-aarch64/morello-stubs-static.d index 53269ac9d2dc4356055c39ef57a585d2c293f7bc..d7627dcbf0571dcb9c8dc5b826385a61941821f0 100644 --- a/ld/testsuite/ld-aarch64/morello-stubs-static.d +++ b/ld/testsuite/ld-aarch64/morello-stubs-static.d @@ -8,29 +8,29 @@
Disassembly of section .text_low:
-00000000000000b0 <foo>: - b0: 9400000c bl e0 <__baz_a64c64_veneer> - b4: c2c1d041 mov c1, c2 - b8: d65f03c0 ret - -00000000000000bc <baz2>: - bc: 14000009 b e0 <__baz_a64c64_veneer> - c0: c2c253c0 ret c30 - c4: 00000000 .* - c8: 1400000a b f0 <__baz_a64c64_veneer+0x10> - cc: d503201f nop - -00000000000000d0 <__baz_veneer>: - d0: 90878010 adrp c16, f000000 <baz3> - d4: 02002610 add c16, c16, #0x9 - d8: c2c21200 br c16 - dc: 00000000 .* - -00000000000000e0 <__baz_a64c64_veneer>: - e0: c2c273e0 bx #4 - e4: 90878010 adrp c16, f000000 <baz3> - e8: 02002610 add c16, c16, #0x9 - ec: c2c21200 br c16 +0000000000010000 <foo>: + 10000: 9400000c bl 10030 <__baz_a64c64_veneer> + 10004: c2c1d041 mov c1, c2 + 10008: d65f03c0 ret + +000000000001000c <baz2>: + 1000c: 14000009 b 10030 <__baz_a64c64_veneer> + 10010: c2c253c0 ret c30 + 10014: 00000000 .* + 10018: 1400000a b 10040 <__baz_a64c64_veneer+0x10> + 1001c: d503201f nop + +0000000000010020 <__baz_veneer>: + 10020: 90877f90 adrp c16, f000000 <baz3> + 10024: 02002610 add c16, c16, #0x9 + 10028: c2c21200 br c16 + 1002c: 00000000 .* + +0000000000010030 <__baz_a64c64_veneer>: + 10030: c2c273e0 bx #4 + 10034: 90877f90 adrp c16, f000000 <baz3> + 10038: 02002610 add c16, c16, #0x9 + 1003c: c2c21200 br c16
Disassembly of section .text_high:
@@ -45,13 +45,13 @@ Disassembly of section .text_high: f000014: d503201f nop
000000000f000018 <__foo_c64a64_veneer>: - f000018: 90f88010 adrp c16, 100000000 <___veneer+0xf0ffffd8> - f00001c: 0202c210 add c16, c16, #0xb0 + f000018: 90f88090 adrp c16, 100010000 <___veneer+0xf100ffd8> + f00001c: 02000210 add c16, c16, #0x0 f000020: c2c21200 br c16 f000024: 00000000 .*
000000000f000028 <___veneer>: - f000028: 90f88010 adrp x16, 0 <foo-0xb0> - f00002c: 9102c210 add x16, x16, #0xb0 + f000028: 90f88090 adrp x16, 10000 <foo> + f00002c: 91000210 add x16, x16, #0x0 f000030: d61f0200 br x16 ... diff --git a/ld/testsuite/ld-aarch64/morello-stubs.d b/ld/testsuite/ld-aarch64/morello-stubs.d index d73bdf6ad90b924d953091422cafa4d4c7cdafd6..d81e58539b5040cc4ec9f25ab04f923da05452a4 100644 --- a/ld/testsuite/ld-aarch64/morello-stubs.d +++ b/ld/testsuite/ld-aarch64/morello-stubs.d @@ -21,7 +21,7 @@ Disassembly of section .text_low: .*: d503201f nop
.* <__baz_veneer>: -.*: 90078010 adrp x16, [0-9a-f]+ <baz3> +.*: 900..... adrp x16, [0-9a-f]+ <baz3> .*: 910...10 add x16, x16, #0x[0-9a-f]+ .*: d61f0200 br x16 ... @@ -39,13 +39,13 @@ Disassembly of section .text_high: .*: d503201f nop
.* <__foo_c64a64_veneer>: -.*: 90f88010 adrp c16, [0-9a-f]+ <.*> +.*: 90f..... adrp c16, [0-9a-f]+ <.*> .*: 020...10 add c16, c16, #0x[0-9a-f]+ .*: c2c21200 br c16 .*: 00000000 .*
.* <___veneer>: -.*: 90f88010 adrp x16, .* <.*> +.*: 90f..... adrp x16, .* <.*> .*: 910...10 add x16, x16, #0x[0-9a-f]+ .*: d61f0200 br x16 ...