Gnu-morello September 2021

gnu-morello@op-lists.linaro.org

2 participants
4 discussions

[PATCH] aarch64: Mark purecap object files with EF_AARCH64_CHERI_PURECAP

by Alex Coplan

Hi all, This simple patch sets the ELF header flag EF_AARCH64_CHERI_PURECAP for purecap Morello object files, as documented in aaelf64-morello (section 4.1): https://github.com/ARM-software/abi-aa/blob/main/aaelf64-morello/aaelf64-mo… Regression tested on aarch64-linux-gnu, OK for users/ARM/morello-binutils-gdb-master? Thanks, Alex gas/ChangeLog: 2021-09-24 Alex Coplan <alex.coplan(a)arm.com> * config/tc-aarch64.c (md_begin): Set the ELF header flag EF_AARCH64_CHERI_PURECAP if we have the C64 extension.

2 years, 7 months

[PATCH] morello: Fix encoding of ldtr/sttr

by Alex Coplan

Hi all, This patch fixes the encoding of the immediate in the A64C ldtr/sttr instructions. Prior to this patch, GAS would accept immediates for these instructions that were not multiples of 16, and would not scale the immediate by 16. Regression tested on aarch64-linux-gnu, OK for users/ARM/morello-binutils-gdb-master? Thanks, Alex --- gas/ChangeLog: 2021-09-24 Alex Coplan <alex.coplan(a)arm.com> * testsuite/gas/aarch64/morello_ldst-c64.d: Update following test + encoding change. * testsuite/gas/aarch64/morello_ldst-invalid.d: New test. * testsuite/gas/aarch64/morello_ldst-invalid.l: New test. * testsuite/gas/aarch64/morello_ldst-invalid.s: New test. * testsuite/gas/aarch64/morello_ldst.d: Update following test + encoding change. * testsuite/gas/aarch64/morello_ldst.s: Update to use valid immediates for ldtr/sttr instructions. opcodes/ChangeLog: 2021-09-24 Alex Coplan <alex.coplan(a)arm.com> * aarch64-tbl.h (aarch64_opcode_table): Update A64C_INSNs ldtr/sttr to take A64C_ADDR_SIMM9 instead of ADDR_SIMM9 operands.

2 years, 7 months

[Committed] morello-binutils: Adjust c64_valid_cap_range calculation

by Matthew Malcomson

This function had a buggy implementation of rounding a value up to a given power of 2. Aligning to a multiple of 16 would align to a multiple of 32 and so on. This was observable when linking object files that had very large objects in them. The compiler would ensure that these objects are large enough that they are exactly representable, but the linker would complain that they are not because the linker asserted extra alignment than the compiler. Here we fix the bug, add a few testcases, and adjust an existing testcase in the area. ############### Attachment also inlined for ease of reply ############### diff --git a/bfd/elfnn-aarch64.c b/bfd/elfnn-aarch64.c index 47001a5bdb91dc3e7341f1cf4068e74b12ff0df6..73ffdad33bc8d5bf9cf2e2d84a606e8d183695f7 100644 --- a/bfd/elfnn-aarch64.c +++ b/bfd/elfnn-aarch64.c @@ -4797,7 +4797,7 @@ exponent (uint64_t len) #undef CAP_MAX_EXPONENT } -#define ONES(x) ((1ULL << ((x) + 1)) - 1) +#define ONES(x) ((1ULL << (x)) - 1) #define ALIGN_UP(x, a) (((x) + ONES (a)) & (~ONES (a))) static bfd_boolean diff --git a/ld/testsuite/ld-aarch64/aarch64-elf.exp b/ld/testsuite/ld-aarch64/aarch64-elf.exp index e9cb95d5e17b43b5ed4fc25e782a9d668c9d785c..228cfe224c57efc1cac6c694d304d8186e8749d6 100644 --- a/ld/testsuite/ld-aarch64/aarch64-elf.exp +++ b/ld/testsuite/ld-aarch64/aarch64-elf.exp @@ -244,6 +244,8 @@ run_dump_test_lp64 "emit-relocs-morello-2" run_dump_test_lp64 "emit-relocs-morello-2-a64c" run_dump_test_lp64 "emit-relocs-morello-3" run_dump_test_lp64 "emit-relocs-morello-3-a64c" +run_dump_test_lp64 "emit-relocs-morello-4" +run_dump_test_lp64 "emit-relocs-morello-5" run_dump_test_lp64 "morello-capinit" run_dump_test_lp64 "morello-stubs" diff --git a/ld/testsuite/ld-aarch64/emit-relocs-morello-4.d b/ld/testsuite/ld-aarch64/emit-relocs-morello-4.d new file mode 100644 index 0000000000000000000000000000000000000000..04cfa79a042a40be2dc3e745437c0ae344b53cc3 --- /dev/null +++ b/ld/testsuite/ld-aarch64/emit-relocs-morello-4.d @@ -0,0 +1,14 @@ +#source: emit-relocs-morello-4.s +#as: -march=morello+c64 +#ld: -static +#readelf: --relocs --syms + + +#... +Relocation section[^\n]*contains 1 entry: +#... +Symbol table[^\n]*contains[^\n]*: + Num: Value Size.* +#... + [0-9]+: [0-9a-f]+0 64016 [^\n]* bigarray +#pass diff --git a/ld/testsuite/ld-aarch64/emit-relocs-morello-4.s b/ld/testsuite/ld-aarch64/emit-relocs-morello-4.s new file mode 100644 index 0000000000000000000000000000000000000000..d91d85ab5eb9080b70e3e70ddc36f2b8e85a2157 --- /dev/null +++ b/ld/testsuite/ld-aarch64/emit-relocs-morello-4.s @@ -0,0 +1,17 @@ +// Checking that having a relocation against very large arrays that are not +// problematic w.r.t. capability bounds representation do not error. +// The below is somthing that requires being padded +.bss +.globl bigarray +.p2align 4 +bigarray: + .zero 64004 + .zero 12 // Tail padding to ensure precise bounds. + .size bigarray, 64016 + +.text +.globl _start +.type _start STT_FUNC +_start: + adrp c0, :got:bigarray + ldr c0, [c0, #:got_lo12:bigarray] diff --git a/ld/testsuite/ld-aarch64/emit-relocs-morello-5.d b/ld/testsuite/ld-aarch64/emit-relocs-morello-5.d new file mode 100644 index 0000000000000000000000000000000000000000..05bbef145e03786dbb489b40441e78fbff69ddb5 --- /dev/null +++ b/ld/testsuite/ld-aarch64/emit-relocs-morello-5.d @@ -0,0 +1,6 @@ +#source: emit-relocs-morello-5.s +#as: -march=morello+c64 +#ld: -static +#error: .*: capability range may exceed object bounds +#error: .*: in function `_start':.* +#error: .*: dangerous relocation: unsupported relocation diff --git a/ld/testsuite/ld-aarch64/emit-relocs-morello-5.s b/ld/testsuite/ld-aarch64/emit-relocs-morello-5.s new file mode 100644 index 0000000000000000000000000000000000000000..0493c26065ced0d117a7ab9ab3969a00ff2045b0 --- /dev/null +++ b/ld/testsuite/ld-aarch64/emit-relocs-morello-5.s @@ -0,0 +1,15 @@ +// Checking that having a relocation against very large arrays whose size can +// not be represented gives the corresponding error. +.bss +.globl bigarray +.p2align 4 +bigarray: + .zero 64004 + .size bigarray, 64004 + +.text +.globl _start +.type _start STT_FUNC +_start: + adrp c0, :got:bigarray + ldr c0, [c0, #:got_lo12:bigarray] diff --git a/ld/testsuite/ld-aarch64/morello-sec-round.d b/ld/testsuite/ld-aarch64/morello-sec-round.d index 00eceb0386a3f8890c2876a4a6bac9569f146e33..b553a604acd92a2b0c5e151546e2c19a04101f70 100644 --- a/ld/testsuite/ld-aarch64/morello-sec-round.d +++ b/ld/testsuite/ld-aarch64/morello-sec-round.d @@ -7,5 +7,5 @@ Idx Name Size VMA LMA File off Algn #... 1 .text_sec 00020004 ...........20000 [0-9a-f]+ [0-9a-f]+ 2\*\*17 CONTENTS, ALLOC, LOAD, READONLY, CODE - 2 \..* [0-9a-f]+ ...........40080 [0-9a-f]+ [0-9a-f]+ .* + 2 \..* [0-9a-f]+ ...........40040 [0-9a-f]+ [0-9a-f]+ .* #pass

2 years, 7 months

[PATCH] aarch64: Correct feature bits for Morello

by Alex Coplan

Hi all, As it stands, the architecture feature bits for Morello include FP16FML (i.e. ARMv8.2-FHM) but not FP16: this is an invalid combination. Looking at the Morello Arm ARM [1], it seems that Morello wants the feature FP16 (ARMv8.2-FP16) but not FP16FML. Regtested on aarch64-none-elf, OK for morello-binutils-gdb-master? Thanks, Alex [1] : https://developer.arm.com/documentation/ddi0606/latest include/ChangeLog: * opcode/aarch64.h (AARCH64_ARCH_MORELLO): Change F16_FML feature bit to F16.

2 years, 7 months

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Gnu-morello September 2021