This includes: - New tests for the new functionality for Morello TLS. - Adding target check for `-shared` to Morello tests that require a target that supports shared libraries. - Tests to ensure the extra error-checking emits errors when needed. - New tests for the new relocations defined for Morello TLS. - Some fixups for existing tests that don't seem like they deserve a separate commit.
Notes about some changes that seem like they require it:
tlsle-symbol-offset testcase: Do not use `-shared` as a linker argument. This testcase is checking for Local-Exec relocations, using these relocations in a shared library is simply not valid. AFAICS there's no need for the `-shared` flag in this testcase, since it's just there to check that the tls LE relocations accept an addend.
This was working before since we did not error on such things, but with the extra hardening that I've added we are now erroring on them.
morello-sec-start_stop-round testcase: We were originally searching for a specific __data_start symbol marking the start of the data section. This was not part of what we actually wanted to test, and the symbol which was printed was different on aarch64-none-linux-gnu. Hence we change our regex to search for any symbol to allow the test to pass on both targets.
morello-tlsie-overflow testcase: This testcase adds some padding in the .text section so that the GOT is very far away from the relocation which attempts to access it. This means that the relocation can not be satisfied and we can check for the resulting error message.
############### Attachment also inlined for ease of reply ###############
diff --git a/ld/testsuite/ld-aarch64/aarch64-elf.exp b/ld/testsuite/ld-aarch64/aarch64-elf.exp index 38ee991e20d048a0359bf01f403e8329003c0aea..a4d5495b22ea9913d4ce6da98aadcb3289b77da2 100644 --- a/ld/testsuite/ld-aarch64/aarch64-elf.exp +++ b/ld/testsuite/ld-aarch64/aarch64-elf.exp @@ -294,7 +294,8 @@ run_dump_test_lp64 "c64-ehdr-sized-reloc"
# Test for morello dynamic relocs can not be written in the usual manner since # we need to specify different `ld` command lines for different objects. -if { [ld_assemble_flags $as -march=morello+c64 $srcdir/$subdir/morello-dynamic-relocs-lib.s tmpdir/morello-dynamic-relocs-lib.o] +if { [check_shared_lib_support] + && [ld_assemble_flags $as -march=morello+c64 $srcdir/$subdir/morello-dynamic-relocs-lib.s tmpdir/morello-dynamic-relocs-lib.o] && [ld_link $ld tmpdir/morello-dynamic-relocs.so "--shared tmpdir/morello-dynamic-relocs-lib.o"] } { run_dump_test_lp64 "morello-dynamic-relocs" run_dump_test_lp64 "morello-dynamic-link-rela-dyn" @@ -310,7 +311,8 @@ if { [ld_assemble_flags $as -march=morello+c64 $srcdir/$subdir/morello-dynamic-r run_dump_test_lp64 "morello-dataptr-code-and-data" }
-if { [ld_assemble_flags $as -march=morello+c64 $srcdir/$subdir/morello-weakdefinitions.s tmpdir/morello-weakdefinitions.o] +if { [check_shared_lib_support] + && [ld_assemble_flags $as -march=morello+c64 $srcdir/$subdir/morello-weakdefinitions.s tmpdir/morello-weakdefinitions.o] && [ld_link $ld tmpdir/morello-weakdefinitions.so "--shared tmpdir/morello-weakdefinitions.o"] } { run_dump_test_lp64 "morello-undefweak-relocs-PDE" } @@ -319,6 +321,14 @@ run_dump_test_lp64 "morello-undefweak-relocs-PIE" run_dump_test_lp64 "morello-undefweak-relocs-static" run_dump_test_lp64 "morello-undefweak-relocs-static-relocs"
+if { [check_shared_lib_support] + && [ld_assemble_flags $as -march=morello+c64 $srcdir/$subdir/tls-shared.s tmpdir/tls-shared.o] + && [ld_link $ld tmpdir/tls-shared.so "-shared tmpdir/tls-shared.o"] } { + run_dump_test_lp64 "morello-tls-pde" + run_dump_test_lp64 "illegal-tlsle-pde" + run_dump_test_lp64 "morello-tlsie-overflow" +} + run_dump_test_lp64 "morello-static-got" run_dump_test_lp64 "morello-dynamic-got" run_dump_test_lp64 "morello-dt-init-fini" @@ -338,6 +348,25 @@ run_dump_test_lp64 "morello-sec-start_stop-round" run_dump_test_lp64 "morello-tlsdesc" run_dump_test_lp64 "morello-tlsdesc-static" run_dump_test_lp64 "morello-tlsdesc-staticpie" +run_dump_test_lp64 "morello-tlsdesc-seen-ie" + +run_dump_test_lp64 "morello-tlsle" +run_dump_test_lp64 "morello-tlsle-pie" +run_dump_test_lp64 "morello-tlsie" +run_dump_test_lp64 "morello-tlsie-pie" +run_dump_test_lp64 "morello-tlsie-shared" + +run_dump_test_lp64 "morello-size-relocs" +run_dump_test_lp64 "morello-size-relocs-pie" +run_dump_test_lp64 "morello-size-relocs-shared" + +run_dump_test_lp64 "morello-illegal-size-relocs" +run_dump_test_lp64 "morello-illegal-size-relocs-pie" +run_dump_test_lp64 "morello-illegal-size-relocs-shared" + +run_dump_test_lp64 "morello-illegal-tls" +run_dump_test_lp64 "morello-illegal-tls-pie" +run_dump_test_lp64 "morello-illegal-tls-shared"
run_dump_test "no-morello-syms-static"
diff --git a/ld/testsuite/ld-aarch64/emit-relocs-morello-2-a64c.d b/ld/testsuite/ld-aarch64/emit-relocs-morello-2-a64c.d index 5d2d90cd271d021ee88f2614a20f4c3a9867a324..b2d16b252fc7fc77ba34239ab9e6eafc48f1e6e8 100644 --- a/ld/testsuite/ld-aarch64/emit-relocs-morello-2-a64c.d +++ b/ld/testsuite/ld-aarch64/emit-relocs-morello-2-a64c.d @@ -1,4 +1,5 @@ #source: emit-relocs-morello-2.s +#target: [check_shared_lib_support] #as: -march=morello+a64c #ld: -shared #objdump: -DR -j .text -j .data -j .got diff --git a/ld/testsuite/ld-aarch64/emit-relocs-morello-2.d b/ld/testsuite/ld-aarch64/emit-relocs-morello-2.d index c5eebec4e1af2e1d6003138da91f912c0db6ac60..4a3c1bb3706be6da70aea4d64be1d34ab0148ee5 100644 --- a/ld/testsuite/ld-aarch64/emit-relocs-morello-2.d +++ b/ld/testsuite/ld-aarch64/emit-relocs-morello-2.d @@ -1,4 +1,5 @@ #source: emit-relocs-morello-2.s +#target: [check_shared_lib_support] #as: -march=morello+c64 --defsym C64MODE=1 #ld: -shared #objdump: -DR -j .text -j .data -j .got diff --git a/ld/testsuite/ld-aarch64/emit-relocs-morello-3-a64c.d b/ld/testsuite/ld-aarch64/emit-relocs-morello-3-a64c.d index f57aa48ca3feb1ab75d6162bb4c882ef0c86309f..3c369a785ca96b21721f5c4bd2d2eed2e3cd45f1 100644 --- a/ld/testsuite/ld-aarch64/emit-relocs-morello-3-a64c.d +++ b/ld/testsuite/ld-aarch64/emit-relocs-morello-3-a64c.d @@ -1,4 +1,5 @@ #source: emit-relocs-morello-3.s +#target: [check_shared_lib_support] #as: -march=morello #ld: -shared #objdump: -DR -j .text -j .data -j .got diff --git a/ld/testsuite/ld-aarch64/emit-relocs-morello-3.d b/ld/testsuite/ld-aarch64/emit-relocs-morello-3.d index 7266ca94469966d71ef5fc3e6104f02125a74a08..c54e232cec92de656b249ae06842f3e8f0b13c1c 100644 --- a/ld/testsuite/ld-aarch64/emit-relocs-morello-3.d +++ b/ld/testsuite/ld-aarch64/emit-relocs-morello-3.d @@ -1,4 +1,5 @@ #source: emit-relocs-morello-3.s +#target: [check_shared_lib_support] #as: -march=morello+c64 --defsym C64MODE=1 #ld: -shared #objdump: -DR -j .text -j .data -j .got diff --git a/ld/testsuite/ld-aarch64/emit-relocs-morello-a64c.d b/ld/testsuite/ld-aarch64/emit-relocs-morello-a64c.d index 35775f72631f84b7494f2aec4918fdffd7fcad45..e7f9c86b456b285daa7c61ebfb75f4db236ffe5d 100644 --- a/ld/testsuite/ld-aarch64/emit-relocs-morello-a64c.d +++ b/ld/testsuite/ld-aarch64/emit-relocs-morello-a64c.d @@ -1,4 +1,5 @@ #source: emit-relocs-morello.s +#target: [check_shared_lib_support] #as: -march=morello #ld: -shared #objdump: -DR -j .text -j .data -j .got diff --git a/ld/testsuite/ld-aarch64/emit-relocs-morello-hidden.d b/ld/testsuite/ld-aarch64/emit-relocs-morello-hidden.d index 9bac38de22516bc2f1679745df483a16a93c0728..35334743999e87da412b9f292cf0332176c87688 100644 --- a/ld/testsuite/ld-aarch64/emit-relocs-morello-hidden.d +++ b/ld/testsuite/ld-aarch64/emit-relocs-morello-hidden.d @@ -1,4 +1,5 @@ #source: emit-relocs-morello-hidden.s +#target: [check_shared_lib_support] #as: -march=morello+c64 #ld: -shared #objdump: -DR -j .got -j .text diff --git a/ld/testsuite/ld-aarch64/emit-relocs-morello.d b/ld/testsuite/ld-aarch64/emit-relocs-morello.d index 1a9be9b60bb9fcf15d74e65e9ebe224ac3d769b8..2db1177ed286c082123a30f9c8a05d27a25a134d 100644 --- a/ld/testsuite/ld-aarch64/emit-relocs-morello.d +++ b/ld/testsuite/ld-aarch64/emit-relocs-morello.d @@ -1,4 +1,5 @@ #source: emit-relocs-morello.s +#target: [check_shared_lib_support] #as: -march=morello+c64 #ld: -shared #objdump: -DR -j .text -j .data -j .got diff --git a/ld/testsuite/ld-aarch64/illegal-tlsle-pde.d b/ld/testsuite/ld-aarch64/illegal-tlsle-pde.d new file mode 100644 index 0000000000000000000000000000000000000000..1fc58fbfc0c1dd748b4eb8175a7ae332ac5c1ae6 --- /dev/null +++ b/ld/testsuite/ld-aarch64/illegal-tlsle-pde.d @@ -0,0 +1,12 @@ +# This test is here to check that if we have a TLS LE relocation against an +# external symbol (e.g. a shared library) the linker complains. Such a +# relocation would not generate anything useful since we don't know which order +# the shared libraries' thread local storage location would be stored at in +# relation to that of other shared libraries. +#name: Illegal :tprel*: relocation. +#as: -march=morello+c64 +#source: illegal-tlsle-pde.s +#ld: tmpdir/tls-shared.so +#error: .*: Local-Exec TLS relocation R_AARCH64_TLSLE_MOVW_TPREL_G0 against non-local symbol `w1' +#error: .*: unresolvable R_AARCH64_TLSLE_MOVW_TPREL_G0 relocation against symbol `w1' +#error: .*: final link failed: bad value diff --git a/ld/testsuite/ld-aarch64/illegal-tlsle-pde.s b/ld/testsuite/ld-aarch64/illegal-tlsle-pde.s new file mode 100644 index 0000000000000000000000000000000000000000..9ed9c17d778d2e0046ec0e1936d90c09cc2d35a2 --- /dev/null +++ b/ld/testsuite/ld-aarch64/illegal-tlsle-pde.s @@ -0,0 +1,23 @@ + # In order to trigger the problem this testcase was added for, we need + # to have a TLS section in the current executable. We already had a + # check for a TLS relocation despite not having a TLS section, but did + # not have a check for a TLS LE relocation against a symbol that is + # external. + .global b + .section .tbss,"awT",%nobits +b: + .zero 65540 + .zero 52 + .size b,100 + + .text + .type a,STT_TLS + .weak a + .align 2 + .p2align 4,,11 + .global _start + .type _start,%function +_start: + # Some TLS LE relocation against a symbol not defined in the current + # executable. + movz x0, #:tprel_g0:w1 diff --git a/ld/testsuite/ld-aarch64/morello-dt-init-fini.d b/ld/testsuite/ld-aarch64/morello-dt-init-fini.d index d530a288b661a056d9d50077c7aa5d45658ebea6..4198f1cfa0a3fa20fe38727be59151d38ca473f9 100644 --- a/ld/testsuite/ld-aarch64/morello-dt-init-fini.d +++ b/ld/testsuite/ld-aarch64/morello-dt-init-fini.d @@ -1,5 +1,6 @@ # Checking that the DT_INIT and DT_FINI entries in the dynamic section include # the LSB when referring to functions which include the LSB. +#target: [check_shared_lib_support] #as: -march=morello+c64 #ld: -shared #readelf: --symbols --dynamic --wide diff --git a/ld/testsuite/ld-aarch64/morello-dynamic-got.d b/ld/testsuite/ld-aarch64/morello-dynamic-got.d index 810eb1033ef7003420791eeeca147170f0f97477..14a9fa0e806844a7654de6d50a545b807f8f9e56 100644 --- a/ld/testsuite/ld-aarch64/morello-dynamic-got.d +++ b/ld/testsuite/ld-aarch64/morello-dynamic-got.d @@ -2,6 +2,7 @@ # observable. We may as well check that the __rela_dyn_start symbol does not # exists. #source: morello-static-got.s +#target: [check_shared_lib_support] #as: -march=morello+c64 #ld: -shared #readelf: --symbols diff --git a/ld/testsuite/ld-aarch64/morello-illegal-size-relocs-pie.d b/ld/testsuite/ld-aarch64/morello-illegal-size-relocs-pie.d new file mode 100644 index 0000000000000000000000000000000000000000..2a152882cfd274b2bfd8cd6c7341ceffbcd3d852 --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-illegal-size-relocs-pie.d @@ -0,0 +1,18 @@ +# Checking that: +# 1) Size relocation is disallowed on a symbol the static linker does not +# know about. +# 2) Relocations against symbols with too large a symbol are caught. +#source: morello-illegal-size-relocs.s +#as: -march=morello+c64 +#ld: -pie +#error: .*: in function `_start': +#error: .*(.text.*): relocation truncated to fit: R_MORELLO_MOVW_SIZE_G0 against symbol `sym2' defined in .data section in .* +#error: .*(.text.*): relocation truncated to fit: R_MORELLO_MOVW_SIZE_G0 against symbol `sym3' defined in .data section in .* +#error: .*(.text.*): relocation truncated to fit: R_MORELLO_MOVW_SIZE_G1 against symbol `sym3' defined in .data section in .* +#error: .*(.text.*): relocation truncated to fit: R_MORELLO_MOVW_SIZE_G0 against symbol `sym4' defined in .data section in .* +#error: .*(.text.*): relocation truncated to fit: R_MORELLO_MOVW_SIZE_G1 against symbol `sym4' defined in .data section in .* +#error: .*(.text.*): relocation truncated to fit: R_MORELLO_MOVW_SIZE_G2 against symbol `sym4' defined in .data section in .* +#error: .*: relocation R_MORELLO_MOVW_SIZE_G0 against `sym1' is disallowed with addend +#error: .*: relocation R_MORELLO_MOVW_SIZE_G0 against `.data' is disallowed with addend +#error: .* relocation R_MORELLO_MOVW_SIZE_G0 against `othersym' must be used against a non-interposable defined symbol +#error: .* final link failed: bad value diff --git a/ld/testsuite/ld-aarch64/morello-illegal-size-relocs-shared.d b/ld/testsuite/ld-aarch64/morello-illegal-size-relocs-shared.d new file mode 100644 index 0000000000000000000000000000000000000000..460ba203d4aa3108f5f91bb57e9340a8e6714a63 --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-illegal-size-relocs-shared.d @@ -0,0 +1,19 @@ +# Checking that: +# 1) Size relocation is disallowed on a symbol the static linker does not +# know about. +# 2) Relocations against symbols with too large a symbol are caught. +#source: morello-illegal-size-relocs.s +#as: -march=morello+c64 +#ld: -shared +#error: .*: relocation R_MORELLO_MOVW_SIZE_G0 against `sym1' must be used against a non-interposable defined symbol +#error: .*: in function `_start': +#error: .*(.text.*): relocation truncated to fit: R_MORELLO_MOVW_SIZE_G0 against symbol `sym2' defined in .data section in .* +#error: .*(.text.*): relocation truncated to fit: R_MORELLO_MOVW_SIZE_G0 against symbol `sym3' defined in .data section in .* +#error: .*(.text.*): relocation truncated to fit: R_MORELLO_MOVW_SIZE_G1 against symbol `sym3' defined in .data section in .* +#error: .*(.text.*): relocation truncated to fit: R_MORELLO_MOVW_SIZE_G0 against symbol `sym4' defined in .data section in .* +#error: .*(.text.*): relocation truncated to fit: R_MORELLO_MOVW_SIZE_G1 against symbol `sym4' defined in .data section in .* +#error: .*(.text.*): relocation truncated to fit: R_MORELLO_MOVW_SIZE_G2 against symbol `sym4' defined in .data section in .* +#error: .*: relocation R_MORELLO_MOVW_SIZE_G0 against `sym1' is disallowed with addend +#error: .*: relocation R_MORELLO_MOVW_SIZE_G0 against `.data' is disallowed with addend +#error: .* relocation R_MORELLO_MOVW_SIZE_G0 against `othersym' must be used against a non-interposable defined symbol +#error: .* final link failed: bad value diff --git a/ld/testsuite/ld-aarch64/morello-illegal-size-relocs.d b/ld/testsuite/ld-aarch64/morello-illegal-size-relocs.d new file mode 100644 index 0000000000000000000000000000000000000000..bb3e8d2ff2c2deda2383de42d9476bbdab8af282 --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-illegal-size-relocs.d @@ -0,0 +1,18 @@ +# Checking that: +# 1) Size relocation is disallowed on a symbol the static linker does not +# know about. +# 2) Relocations against symbols with too large a symbol are caught. +#source: morello-illegal-size-relocs.s +#as: -march=morello+c64 +#ld: +#error: .*: in function `_start': +#error: .*(.text.*): relocation truncated to fit: R_MORELLO_MOVW_SIZE_G0 against symbol `sym2' defined in .data section in .* +#error: .*(.text.*): relocation truncated to fit: R_MORELLO_MOVW_SIZE_G0 against symbol `sym3' defined in .data section in .* +#error: .*(.text.*): relocation truncated to fit: R_MORELLO_MOVW_SIZE_G1 against symbol `sym3' defined in .data section in .* +#error: .*(.text.*): relocation truncated to fit: R_MORELLO_MOVW_SIZE_G0 against symbol `sym4' defined in .data section in .* +#error: .*(.text.*): relocation truncated to fit: R_MORELLO_MOVW_SIZE_G1 against symbol `sym4' defined in .data section in .* +#error: .*(.text.*): relocation truncated to fit: R_MORELLO_MOVW_SIZE_G2 against symbol `sym4' defined in .data section in .* +#error: .*: relocation R_MORELLO_MOVW_SIZE_G0 against `sym1' is disallowed with addend +#error: .*: relocation R_MORELLO_MOVW_SIZE_G0 against `.data' is disallowed with addend +#error: .* relocation R_MORELLO_MOVW_SIZE_G0 against `othersym' must be used against a non-interposable defined symbol +#error: .* final link failed: bad value diff --git a/ld/testsuite/ld-aarch64/morello-illegal-size-relocs.s b/ld/testsuite/ld-aarch64/morello-illegal-size-relocs.s new file mode 100644 index 0000000000000000000000000000000000000000..6416fca53a6d226f209b16c0c1ac235c2ed151f7 --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-illegal-size-relocs.s @@ -0,0 +1,66 @@ +# This is illegal for a shared object since this symbol is interposable. + .data + .globl sym1 + .size sym1, 0xa0a0 +sym1: + .xword 0 + .globl sym2 + .hidden sym2 + .size sym2, 0xa0a0b0b0 +sym2: + .xword 0 + .globl sym3 + .hidden sym3 + .size sym3, 0xa0a0b0b0c0c0 +sym3: + .xword 0 + .globl sym4 + .hidden sym4 + .size sym4, 0xa0a0b0b0c0c0d0d0 +sym4: + .xword 0 + .size localsym, 0xa0a0 +localsym: + .xword 0 + + .weak othersym + + .text + .globl _start + .type _start, STT_FUNC +_start: + movk x12, #:size_g0:sym1 + + # Too large symbols, n.b. we include some relocations which are not too large + # since they will simply not get an error on them. + movk x12, #:size_g0:sym2 + movk x12, #:size_g1:sym2 + movk x12, #:size_g2:sym2 + movk x12, #:size_g3:sym2 + + movk x12, #:size_g0:sym3 + movk x12, #:size_g1:sym3 + movk x12, #:size_g2:sym3 + movk x12, #:size_g3:sym3 + + movk x12, #:size_g0:sym4 + movk x12, #:size_g1:sym4 + movk x12, #:size_g2:sym4 + movk x12, #:size_g3:sym4 + + # Relocation with an addend disallowed. + movk x12, #:size_g0:sym1+10 + # N.b. this currently complains about a relocation against `.data` with an + # addend. That is due to a GAS bug that we need to fix. Once that GAS bug + # has been fixed (i.e. we should not emit relocations against a section symbol + # plus addend) the error message that this testcase should check against should + # be changed. At the same time it would probably be nice to put extra tests + # into morello-size-relocs.s checking that local symbols work just fine. + # + # Luckily, the transformation from `localsym` to `.data` isn't problematic + # since the section symbol is local and the point of including this line is + # to check that our obtaining of local symbols names is correct. + movk x12, #:size_g0:localsym+10 + + # Relocation againts undefweak symbol disallowed. + movk x12, #:size_g0:othersym diff --git a/ld/testsuite/ld-aarch64/morello-illegal-tls-pde.d b/ld/testsuite/ld-aarch64/morello-illegal-tls-pde.d new file mode 100644 index 0000000000000000000000000000000000000000..827e804e623de2b798c647fb04065772ac8fed32 --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-illegal-tls-pde.d @@ -0,0 +1,6 @@ +#as: -march=morello+c64 +#ld: tmpdir/morello-tls-shared.so + +#error: .*: relocation R_MORELLO_MOVW_SIZE_G1 against `w1' must be used against a non-interposable defined symbol +#error: .*: unresolvable R_MORELLO_MOVW_SIZE_G1 relocation against symbol `w1' +#error: .*: final link failed: bad value diff --git a/ld/testsuite/ld-aarch64/morello-illegal-tls-pde.s b/ld/testsuite/ld-aarch64/morello-illegal-tls-pde.s new file mode 100644 index 0000000000000000000000000000000000000000..b415e5a0d7e8d0622c699d2b9530f2439f62eb89 --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-illegal-tls-pde.s @@ -0,0 +1,33 @@ + .section .tbss,"awT",@nobits + .align 2 + .type w, %object + .size w, 4 +w: + .zero 4 + .align 2 + .global exec_sym + .type exec_sym, %object + .size exec_sym, 4 +exec_sym: + .zero 4 + + .text + .align 2 + .global _start + .type _start, %function +_start: + ret +load_w: + # A local exec load of a symbol defined in a different shared library + # should be an error. + mrs c0, ctpidr_el0 + movz x1, #:tprel_g1:w1 + movk x1, #:tprel_g0_nc:w1 + add c0, c0, x1 + movz x1, #:size_g1:w1 + movk x1, #:size_g0_nc:w1 + scbnds c0, c0, x1 + ldr w0, [c0] + ret + .size _start, .-_start + diff --git a/ld/testsuite/ld-aarch64/morello-illegal-tls-pie.d b/ld/testsuite/ld-aarch64/morello-illegal-tls-pie.d new file mode 100644 index 0000000000000000000000000000000000000000..082765cffe02fc15f4f3fbd2eb61dae1852accb0 --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-illegal-tls-pie.d @@ -0,0 +1,10 @@ +# Check that TLS relocations with an addend are disallowed. +#source: morello-illegal-tls.s +#as: -march=morello+c64 +#ld: -pie +#error: .*(.text.*): relocation R_MORELLO_TLSIE_ADR_GOTTPREL_PAGE20 against `a' is disallowed with addend +#error: .*(.text.*): relocation R_MORELLO_TLSIE_ADD_LO12 against `a' is disallowed with addend +#error: .*(.text.*): relocation R_MORELLO_TLSDESC_ADR_PAGE20 against `a' is disallowed with addend +#error: .*(.text.*): relocation R_MORELLO_TLSDESC_LD128_LO12 against `a' is disallowed with addend +#error: .*(.text.*): relocation R_AARCH64_TLSDESC_ADD_LO12 against `a' is disallowed with addend +#error: .*(.text.*): relocation R_MORELLO_TLSDESC_CALL against `a' is disallowed with addend diff --git a/ld/testsuite/ld-aarch64/morello-illegal-tls-shared.d b/ld/testsuite/ld-aarch64/morello-illegal-tls-shared.d new file mode 100644 index 0000000000000000000000000000000000000000..9034ed909f62f242963d8ec739009973378aa4d2 --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-illegal-tls-shared.d @@ -0,0 +1,10 @@ +# Check that TLS relocations with an addend are disallowed. +#source: morello-illegal-tls.s +#as: -march=morello+c64 +#ld: -shared +#error: .*(.text.*): relocation R_MORELLO_TLSIE_ADR_GOTTPREL_PAGE20 against `a' is disallowed with addend +#error: .*(.text.*): relocation R_MORELLO_TLSIE_ADD_LO12 against `a' is disallowed with addend +#error: .*(.text.*): relocation R_MORELLO_TLSDESC_ADR_PAGE20 against `a' is disallowed with addend +#error: .*(.text.*): relocation R_MORELLO_TLSDESC_LD128_LO12 against `a' is disallowed with addend +#error: .*(.text.*): relocation R_AARCH64_TLSDESC_ADD_LO12 against `a' is disallowed with addend +#error: .*(.text.*): relocation R_MORELLO_TLSDESC_CALL against `a' is disallowed with addend diff --git a/ld/testsuite/ld-aarch64/morello-illegal-tls.d b/ld/testsuite/ld-aarch64/morello-illegal-tls.d new file mode 100644 index 0000000000000000000000000000000000000000..f8480b535e1c933ae62de79b92db873a7298f717 --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-illegal-tls.d @@ -0,0 +1,10 @@ +# Check that TLS relocations with an addend are disallowed. +#as: -march=morello+c64 +#ld: +#error: .*(.text.*): relocation R_MORELLO_TLSIE_ADR_GOTTPREL_PAGE20 against `a' is disallowed with addend +#error: .*(.text.*): relocation R_MORELLO_TLSIE_ADD_LO12 against `a' is disallowed with addend +#error: .*(.text.*): relocation R_MORELLO_TLSDESC_ADR_PAGE20 against `a' is disallowed with addend +#error: .*(.text.*): relocation R_MORELLO_TLSDESC_LD128_LO12 against `a' is disallowed with addend +#error: .*(.text.*): relocation R_AARCH64_TLSDESC_ADD_LO12 against `a' is disallowed with addend +#error: .*(.text.*): relocation R_MORELLO_TLSDESC_CALL against `a' is disallowed with addend + diff --git a/ld/testsuite/ld-aarch64/morello-illegal-tls.s b/ld/testsuite/ld-aarch64/morello-illegal-tls.s new file mode 100644 index 0000000000000000000000000000000000000000..8b1816d0aac6c08b284b7c014f64df147ac26b74 --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-illegal-tls.s @@ -0,0 +1,35 @@ + .global a + .section .tbss,"awT",%nobits +a: + .zero 65540 + .zero 52 + .size a,65592 + +# Compute the address of an integer within structure a, padded +# by an array of size 48 + + .text + .align 2 + .p2align 4,,11 + .global _start + .type _start,%function +_start: +# Should not allow a TLS relocation with an addend. +# This particular case is tricky because it can get relaxed to a non-TLS +# relocation against the data stubs (when in an executable). +# That means that the place where we check in binutils should be before this +# relaxation (which is not the usual place to check such things). + adrp c2, :gottprel:a+10 + add c2, c2, :gottprel_lo12:a+10 + adrp c0, :tlsdesc:a+10 + ldr c1, [c0, #:tlsdesc_lo12:a+10] + add c0, c0, #:tlsdesc_lo12:a+10 + .tlsdesccall a+10 + blr c1 + # N.b. the below (Local-Exec relocations with an addend) are accepted. + # We check this by observing that we don't get an error message produced + # for them. + movz x2, #:tprel_g1:a+10 + movk x2, #:tprel_g0_nc:a+10 + + movz x2, #:tprel_g1:undefinedsym diff --git a/ld/testsuite/ld-aarch64/morello-sec-start_stop-round.d b/ld/testsuite/ld-aarch64/morello-sec-start_stop-round.d index 3987696e5ab864a4ef1f57016eb9a87f2849f8a2..f092f0d1c8424d8695239c2daf743a4d438988d4 100644 --- a/ld/testsuite/ld-aarch64/morello-sec-start_stop-round.d +++ b/ld/testsuite/ld-aarch64/morello-sec-start_stop-round.d @@ -7,7 +7,7 @@
Disassembly of section .data:
-[0-9a-f]+ <__data_start>: +[0-9a-f]+ <.*>: #record: START_LIBC_ADDR .*: ([0-9a-f]+) .* .*: 00000000 .* diff --git a/ld/testsuite/ld-aarch64/morello-size-relocs-pie.d b/ld/testsuite/ld-aarch64/morello-size-relocs-pie.d new file mode 100644 index 0000000000000000000000000000000000000000..1db5bab223324170dc8c2f8b5f26ce647092e71c --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-size-relocs-pie.d @@ -0,0 +1,69 @@ +# Checking that: +# 1) Size relocation is handled. +# 2) Size relocation inserts correct size. +#source: morello-size-relocs.s +#as: -march=morello+c64 +#ld: -pie +#objdump: -t -d + +.*: file format .* + +SYMBOL TABLE: +#... +.* g .data 000000000000a0a0 .hidden sym1 +#... +.* g .data a0a0b0b0c0c0d0d0 .hidden sym4 +.* g .data 0000a0a0b0b0c0c0 .hidden sym3 +#... +.* g .data 00000000a0a0b0b0 .hidden sym2 +#... + + +Disassembly of section .text: + +.* <_start>: + +[0-9a-f]+: .* movk x12, #0xa0a0 + +[0-9a-f]+: .* movk x12, #0xa0a0 + +[0-9a-f]+: .* movk x12, #0x0, lsl #16 + +[0-9a-f]+: .* movk x12, #0x0, lsl #16 + +[0-9a-f]+: .* movk x12, #0x0, lsl #32 + +[0-9a-f]+: .* movk x12, #0x0, lsl #32 + +[0-9a-f]+: .* movk x12, #0x0, lsl #48 + +[0-9a-f]+: .* movk x13, #0xb0b0 + +[0-9a-f]+: .* movk x13, #0xa0a0, lsl #16 + +[0-9a-f]+: .* movk x13, #0xa0a0, lsl #16 + +[0-9a-f]+: .* movk x13, #0x0, lsl #32 + +[0-9a-f]+: .* movk x13, #0x0, lsl #32 + +[0-9a-f]+: .* movk x13, #0x0, lsl #48 + +[0-9a-f]+: .* movk x13, #0xc0c0 + +[0-9a-f]+: .* movk x13, #0xb0b0, lsl #16 + +[0-9a-f]+: .* movk x13, #0xa0a0, lsl #32 + +[0-9a-f]+: .* movk x13, #0xa0a0, lsl #32 + +[0-9a-f]+: .* movk x13, #0x0, lsl #48 + +[0-9a-f]+: .* movk x13, #0xd0d0 + +[0-9a-f]+: .* movk x13, #0xc0c0, lsl #16 + +[0-9a-f]+: .* movk x13, #0xb0b0, lsl #32 + +[0-9a-f]+: .* movk x13, #0xa0a0, lsl #48 + +[0-9a-f]+: .* mov x12, #0xa0a0 // #41120 + +[0-9a-f]+: .* mov x12, #0xa0a0 // #41120 + +[0-9a-f]+: .* movz x12, #0x0, lsl #16 + +[0-9a-f]+: .* movz x12, #0x0, lsl #16 + +[0-9a-f]+: .* movz x12, #0x0, lsl #32 + +[0-9a-f]+: .* movz x12, #0x0, lsl #32 + +[0-9a-f]+: .* movz x12, #0x0, lsl #48 + +[0-9a-f]+: .* mov x13, #0xb0b0 // #45232 + +[0-9a-f]+: .* mov x13, #0xa0a00000 // #2694840320 + +[0-9a-f]+: .* mov x13, #0xa0a00000 // #2694840320 + +[0-9a-f]+: .* movz x13, #0x0, lsl #32 + +[0-9a-f]+: .* movz x13, #0x0, lsl #32 + +[0-9a-f]+: .* movz x13, #0x0, lsl #48 + +[0-9a-f]+: .* mov x13, #0xc0c0 // #49344 + +[0-9a-f]+: .* mov x13, #0xb0b00000 // #2964324352 + +[0-9a-f]+: .* mov x13, #0xa0a000000000 // #176609055211520 + +[0-9a-f]+: .* mov x13, #0xa0a000000000 // #176609055211520 + +[0-9a-f]+: .* movz x13, #0x0, lsl #48 + +[0-9a-f]+: .* mov x13, #0xd0d0 // #53456 + +[0-9a-f]+: .* mov x13, #0xc0c00000 // #3233808384 + +[0-9a-f]+: .* mov x13, #0xb0b000000000 // #194269960732672 + +[0-9a-f]+: .* mov x13, #0xa0a0000000000000 // #-6872493031367376896 + diff --git a/ld/testsuite/ld-aarch64/morello-size-relocs-shared.d b/ld/testsuite/ld-aarch64/morello-size-relocs-shared.d new file mode 100644 index 0000000000000000000000000000000000000000..68b188fff86a706ac7f76074e55ecc9705680d58 --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-size-relocs-shared.d @@ -0,0 +1,67 @@ +# Checking that: +# 1) Size relocation is handled. +# 2) Size relocation inserts correct size. +#source: morello-size-relocs.s +#as: -march=morello+c64 +#ld: -shared +#objdump: -t -d + +.*: file format .* + +SYMBOL TABLE: +#... +.* l .data 000000000000a0a0 sym1 +.* +.* l .data a0a0b0b0c0c0d0d0 sym4 +.* l .data 0000a0a0b0b0c0c0 sym3 +.* l .data 00000000a0a0b0b0 sym2 +#... + + +Disassembly of section .text: + +.* <_start>: + +[0-9a-f]+: .* movk x12, #0xa0a0 + +[0-9a-f]+: .* movk x12, #0xa0a0 + +[0-9a-f]+: .* movk x12, #0x0, lsl #16 + +[0-9a-f]+: .* movk x12, #0x0, lsl #16 + +[0-9a-f]+: .* movk x12, #0x0, lsl #32 + +[0-9a-f]+: .* movk x12, #0x0, lsl #32 + +[0-9a-f]+: .* movk x12, #0x0, lsl #48 + +[0-9a-f]+: .* movk x13, #0xb0b0 + +[0-9a-f]+: .* movk x13, #0xa0a0, lsl #16 + +[0-9a-f]+: .* movk x13, #0xa0a0, lsl #16 + +[0-9a-f]+: .* movk x13, #0x0, lsl #32 + +[0-9a-f]+: .* movk x13, #0x0, lsl #32 + +[0-9a-f]+: .* movk x13, #0x0, lsl #48 + +[0-9a-f]+: .* movk x13, #0xc0c0 + +[0-9a-f]+: .* movk x13, #0xb0b0, lsl #16 + +[0-9a-f]+: .* movk x13, #0xa0a0, lsl #32 + +[0-9a-f]+: .* movk x13, #0xa0a0, lsl #32 + +[0-9a-f]+: .* movk x13, #0x0, lsl #48 + +[0-9a-f]+: .* movk x13, #0xd0d0 + +[0-9a-f]+: .* movk x13, #0xc0c0, lsl #16 + +[0-9a-f]+: .* movk x13, #0xb0b0, lsl #32 + +[0-9a-f]+: .* movk x13, #0xa0a0, lsl #48 + +[0-9a-f]+: .* mov x12, #0xa0a0 // #41120 + +[0-9a-f]+: .* mov x12, #0xa0a0 // #41120 + +[0-9a-f]+: .* movz x12, #0x0, lsl #16 + +[0-9a-f]+: .* movz x12, #0x0, lsl #16 + +[0-9a-f]+: .* movz x12, #0x0, lsl #32 + +[0-9a-f]+: .* movz x12, #0x0, lsl #32 + +[0-9a-f]+: .* movz x12, #0x0, lsl #48 + +[0-9a-f]+: .* mov x13, #0xb0b0 // #45232 + +[0-9a-f]+: .* mov x13, #0xa0a00000 // #2694840320 + +[0-9a-f]+: .* mov x13, #0xa0a00000 // #2694840320 + +[0-9a-f]+: .* movz x13, #0x0, lsl #32 + +[0-9a-f]+: .* movz x13, #0x0, lsl #32 + +[0-9a-f]+: .* movz x13, #0x0, lsl #48 + +[0-9a-f]+: .* mov x13, #0xc0c0 // #49344 + +[0-9a-f]+: .* mov x13, #0xb0b00000 // #2964324352 + +[0-9a-f]+: .* mov x13, #0xa0a000000000 // #176609055211520 + +[0-9a-f]+: .* mov x13, #0xa0a000000000 // #176609055211520 + +[0-9a-f]+: .* movz x13, #0x0, lsl #48 + +[0-9a-f]+: .* mov x13, #0xd0d0 // #53456 + +[0-9a-f]+: .* mov x13, #0xc0c00000 // #3233808384 + +[0-9a-f]+: .* mov x13, #0xb0b000000000 // #194269960732672 + +[0-9a-f]+: .* mov x13, #0xa0a0000000000000 // #-6872493031367376896 diff --git a/ld/testsuite/ld-aarch64/morello-size-relocs.d b/ld/testsuite/ld-aarch64/morello-size-relocs.d new file mode 100644 index 0000000000000000000000000000000000000000..0de1d678b4441348ffecf40cd7276a81b182f158 --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-size-relocs.d @@ -0,0 +1,67 @@ +# Checking that: +# 1) Size relocation is handled. +# 2) Size relocation inserts correct size. +#as: -march=morello+c64 +#ld: +#objdump: -t -d + +.*: file format .* + +SYMBOL TABLE: +#... +.* g .data 000000000000a0a0 .hidden sym1 +#... +.* g .data a0a0b0b0c0c0d0d0 .hidden sym4 +.* g .data 0000a0a0b0b0c0c0 .hidden sym3 +#... +.* g .data 00000000a0a0b0b0 .hidden sym2 +#... + + +Disassembly of section .text: + +.* <_start>: + +[0-9a-f]+: .* movk x12, #0xa0a0 + +[0-9a-f]+: .* movk x12, #0xa0a0 + +[0-9a-f]+: .* movk x12, #0x0, lsl #16 + +[0-9a-f]+: .* movk x12, #0x0, lsl #16 + +[0-9a-f]+: .* movk x12, #0x0, lsl #32 + +[0-9a-f]+: .* movk x12, #0x0, lsl #32 + +[0-9a-f]+: .* movk x12, #0x0, lsl #48 + +[0-9a-f]+: .* movk x13, #0xb0b0 + +[0-9a-f]+: .* movk x13, #0xa0a0, lsl #16 + +[0-9a-f]+: .* movk x13, #0xa0a0, lsl #16 + +[0-9a-f]+: .* movk x13, #0x0, lsl #32 + +[0-9a-f]+: .* movk x13, #0x0, lsl #32 + +[0-9a-f]+: .* movk x13, #0x0, lsl #48 + +[0-9a-f]+: .* movk x13, #0xc0c0 + +[0-9a-f]+: .* movk x13, #0xb0b0, lsl #16 + +[0-9a-f]+: .* movk x13, #0xa0a0, lsl #32 + +[0-9a-f]+: .* movk x13, #0xa0a0, lsl #32 + +[0-9a-f]+: .* movk x13, #0x0, lsl #48 + +[0-9a-f]+: .* movk x13, #0xd0d0 + +[0-9a-f]+: .* movk x13, #0xc0c0, lsl #16 + +[0-9a-f]+: .* movk x13, #0xb0b0, lsl #32 + +[0-9a-f]+: .* movk x13, #0xa0a0, lsl #48 + +[0-9a-f]+: .* mov x12, #0xa0a0 // #41120 + +[0-9a-f]+: .* mov x12, #0xa0a0 // #41120 + +[0-9a-f]+: .* movz x12, #0x0, lsl #16 + +[0-9a-f]+: .* movz x12, #0x0, lsl #16 + +[0-9a-f]+: .* movz x12, #0x0, lsl #32 + +[0-9a-f]+: .* movz x12, #0x0, lsl #32 + +[0-9a-f]+: .* movz x12, #0x0, lsl #48 + +[0-9a-f]+: .* mov x13, #0xb0b0 // #45232 + +[0-9a-f]+: .* mov x13, #0xa0a00000 // #2694840320 + +[0-9a-f]+: .* mov x13, #0xa0a00000 // #2694840320 + +[0-9a-f]+: .* movz x13, #0x0, lsl #32 + +[0-9a-f]+: .* movz x13, #0x0, lsl #32 + +[0-9a-f]+: .* movz x13, #0x0, lsl #48 + +[0-9a-f]+: .* mov x13, #0xc0c0 // #49344 + +[0-9a-f]+: .* mov x13, #0xb0b00000 // #2964324352 + +[0-9a-f]+: .* mov x13, #0xa0a000000000 // #176609055211520 + +[0-9a-f]+: .* mov x13, #0xa0a000000000 // #176609055211520 + +[0-9a-f]+: .* movz x13, #0x0, lsl #48 + +[0-9a-f]+: .* mov x13, #0xd0d0 // #53456 + +[0-9a-f]+: .* mov x13, #0xc0c00000 // #3233808384 + +[0-9a-f]+: .* mov x13, #0xb0b000000000 // #194269960732672 + +[0-9a-f]+: .* mov x13, #0xa0a0000000000000 // #-6872493031367376896 diff --git a/ld/testsuite/ld-aarch64/morello-size-relocs.s b/ld/testsuite/ld-aarch64/morello-size-relocs.s new file mode 100644 index 0000000000000000000000000000000000000000..78954660408609407f9ececce5a290e788fa1f31 --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-size-relocs.s @@ -0,0 +1,103 @@ +# Ensure that the size relocations are correctly handled. +# Here we just test that each of the valid kind of size relocations is handled +# well. +# +# Description of the testcase: +# Set of two chunks. Fist tests `movk`, second tests `movz`. +# +# Each chunk has 4 subparts. Those subparts check all viable relocations for +# a size which fits into the bottom 16, 32, 48, and 64 bits respectively. +# +# We use .hidden in order to allow the -shared test to test that things work +# fine there too (since this relocation is only allowed on a symbol which is +# known to resolve locally). + .data + .globl sym1 + .hidden sym1 + .size sym1, 0xa0a0 +sym1: + .xword 0 + .globl sym2 + .hidden sym2 + .size sym2, 0xa0a0b0b0 +sym2: + .xword 0 + .globl sym3 + .hidden sym3 + .size sym3, 0xa0a0b0b0c0c0 +sym3: + .xword 0 + .globl sym4 + .hidden sym4 + .size sym4, 0xa0a0b0b0c0c0d0d0 +sym4: + .xword 0 + .text + .globl _start + .type _start, STT_FUNC +_start: + movk x12, #:size_g0:sym1 + movk x12, #:size_g0_nc:sym1 + movk x12, #:size_g1:sym1 + movk x12, #:size_g1_nc:sym1 + movk x12, #:size_g2:sym1 + movk x12, #:size_g2_nc:sym1 + movk x12, #:size_g3:sym1 + + # movk x13, #:size_g0:sym2 + movk x13, #:size_g0_nc:sym2 + movk x13, #:size_g1:sym2 + movk x13, #:size_g1_nc:sym2 + movk x13, #:size_g2:sym2 + movk x13, #:size_g2_nc:sym2 + movk x13, #:size_g3:sym2 + + # movk x13, #:size_g0:sym3 + movk x13, #:size_g0_nc:sym3 + # movk x13, #:size_g1:sym3 + movk x13, #:size_g1_nc:sym3 + movk x13, #:size_g2:sym3 + movk x13, #:size_g2_nc:sym3 + movk x13, #:size_g3:sym3 + + # movk x13, #:size_g0:sym4 + movk x13, #:size_g0_nc:sym4 + # movk x13, #:size_g1:sym4 + movk x13, #:size_g1_nc:sym4 + # movk x13, #:size_g2:sym4 + movk x13, #:size_g2_nc:sym4 + movk x13, #:size_g3:sym4 + + + movz x12, #:size_g0:sym1 + movz x12, #:size_g0_nc:sym1 + movz x12, #:size_g1:sym1 + movz x12, #:size_g1_nc:sym1 + movz x12, #:size_g2:sym1 + movz x12, #:size_g2_nc:sym1 + movz x12, #:size_g3:sym1 + + # movz x13, #:size_g0:sym2 + movz x13, #:size_g0_nc:sym2 + movz x13, #:size_g1:sym2 + movz x13, #:size_g1_nc:sym2 + movz x13, #:size_g2:sym2 + movz x13, #:size_g2_nc:sym2 + movz x13, #:size_g3:sym2 + + # movz x13, #:size_g0:sym3 + movz x13, #:size_g0_nc:sym3 + # movz x13, #:size_g1:sym3 + movz x13, #:size_g1_nc:sym3 + movz x13, #:size_g2:sym3 + movz x13, #:size_g2_nc:sym3 + movz x13, #:size_g3:sym3 + + # movz x13, #:size_g0:sym4 + movz x13, #:size_g0_nc:sym4 + # movz x13, #:size_g1:sym4 + movz x13, #:size_g1_nc:sym4 + # movz x13, #:size_g2:sym4 + movz x13, #:size_g2_nc:sym4 + movz x13, #:size_g3:sym4 + diff --git a/ld/testsuite/ld-aarch64/morello-stubs.d b/ld/testsuite/ld-aarch64/morello-stubs.d index d81e58539b5040cc4ec9f25ab04f923da05452a4..0f78ff21eeefe3d7f505683dcb7091ccd5ded2c7 100644 --- a/ld/testsuite/ld-aarch64/morello-stubs.d +++ b/ld/testsuite/ld-aarch64/morello-stubs.d @@ -1,4 +1,5 @@ #source: morello-stubs.s +#target: [check_shared_lib_support] #as: #ld: -shared -T morello-stubs.ld #objdump: -DR -j .text_low -j .text_high -j .got.plt -j .plt diff --git a/ld/testsuite/ld-aarch64/morello-tls-pde.d b/ld/testsuite/ld-aarch64/morello-tls-pde.d new file mode 100644 index 0000000000000000000000000000000000000000..7568e9fce4b957dc46b6e5b563ea2ceb031585c1 --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-tls-pde.d @@ -0,0 +1,83 @@ +# Ensure the following things for dynamically linked PDE's: +# 1) We relax the global dynamic reference to an external value to an IE +# reference. +# 2) We relax an IE reference to a value defined in the executable down to an +# LE reference (with the correct location and emition of our data stub). +# 3) LE relocation is handled without messing up. +#as: -march=morello+c64 +#ld: tmpdir/tls-shared.so +#objdump: -DR -j .text -j .got -j .rodata + +.*: +file format .* + + +Disassembly of section .text: + +[0-9a-f]+ <_start>: + +[0-9a-f]+: c2c253c0 ret c30 + +[0-9a-f]+ <load_w>: + +[0-9a-f]+: c29bd040 mrs c0, ctpidr_el0 + +[0-9a-f]+: d2a00001 movz x1, #0x0, lsl #16 + +[0-9a-f]+: f2800401 movk x1, #0x20 + +[0-9a-f]+: c2a16000 add c0, c0, x1, uxtx + +[0-9a-f]+: d2a00001 movz x1, #0x0, lsl #16 + +[0-9a-f]+: f2800081 movk x1, #0x4 + +[0-9a-f]+: c2c10000 scbnds c0, c0, x1 + +[0-9a-f]+: b9400000 ldr w0, [c0] + +[0-9a-f]+: c2c253c0 ret c30 + +[0-9a-f]+ <load_w_ie>: +#record: RODATA_PAGE + +[0-9a-f]+: .* adrp c0, ([0-9a-f]+) .* +#record: W_IE_OFF + +[0-9a-f]+: .* add c0, c0, #0x([0-9a-f]+) + +[0-9a-f]+: a9400402 ldp x2, x1, [c0] + +[0-9a-f]+: c29bd040 mrs c0, ctpidr_el0 + +[0-9a-f]+: c2a26000 add c0, c0, x2, uxtx + +[0-9a-f]+: c2c10000 scbnds c0, c0, x1 + +[0-9a-f]+: b9400000 ldr w0, [c0] + +[0-9a-f]+: c2c253c0 ret c30 + +[0-9a-f]+ <load_w1>: +#record: GOTPAGE + +[0-9a-f]+: .* adrp c0, ([0-9a-f]+) .* +#record: W1_OFF + +[0-9a-f]+: .* add c0, c0, #0x([0-9a-f]+) + +[0-9a-f]+: a9400402 ldp x2, x1, [c0] + +[0-9a-f]+: c29bd040 mrs c0, ctpidr_el0 + +[0-9a-f]+: c2a26000 add c0, c0, x2, uxtx + +[0-9a-f]+: c2c10000 scbnds c0, c0, x1 + +[0-9a-f]+: b9400000 ldr w0, [c0] + +[0-9a-f]+: c2c253c0 ret c30 + +[0-9a-f]+ <load_w2>: + +[0-9a-f]+: c29bd042 mrs c2, ctpidr_el0 +#check: PAGE string tolower $GOTPAGE + +[0-9a-f]+: .* adrp c0, PAGE .* +#record: W2_OFF + +[0-9a-f]+: .* add c0, c0, #0x([0-9a-f]+) + +[0-9a-f]+: a9400400 ldp x0, x1, [c0] + +[0-9a-f]+: c2a06040 add c0, c2, x0, uxtx + +[0-9a-f]+: c2c10000 scbnds c0, c0, x1 + +[0-9a-f]+: b9400000 ldr w0, [c0] + +[0-9a-f]+: c2c253c0 ret c30 + +Disassembly of section .rodata: + +#check: W_DATA_LOC aarch64_page_plus_offset $RODATA_PAGE $W_IE_OFF +[0-9a-f]+ <.rodata>: + +W_DATA_LOC: 00000020 udf #32 + +[0-9a-f]+: 00000000 udf #0 + +[0-9a-f]+: 00000004 udf #4 + +[0-9a-f]+: 00000000 udf #0 + +Disassembly of section .got: + +#check: W1_LOC aarch64_page_plus_offset $GOTPAGE $W1_OFF +#check: W2_LOC aarch64_page_plus_offset $GOTPAGE $W2_OFF +[0-9a-f]+ <.*>: +.* + ... + W1_LOC: R_MORELLO_TPREL128 w1 + W2_LOC: R_MORELLO_TPREL128 w2 diff --git a/ld/testsuite/ld-aarch64/morello-tls-pde.s b/ld/testsuite/ld-aarch64/morello-tls-pde.s new file mode 100644 index 0000000000000000000000000000000000000000..4c423937bc2ef8878db2de5739f6e6edf3a7cb8a --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-tls-pde.s @@ -0,0 +1,69 @@ + .section .tbss,"awT",@nobits + .align 2 + .type w, %object + .size w, 4 +w: + .zero 4 + .align 2 + .global exec_sym + .type exec_sym, %object + .size exec_sym, 4 +exec_sym: + .zero 4 + + .text + .align 2 + .global _start + .type _start, %function +_start: + ret +load_w: + # A local exec load of a local symbol. + # Should stay the same. + mrs c0, ctpidr_el0 + movz x1, #:tprel_g1:w + movk x1, #:tprel_g0_nc:w + add c0, c0, x1 + movz x1, #:size_g1:w + movk x1, #:size_g0_nc:w + scbnds c0, c0, x1 + ldr w0, [c0] + ret +load_w_ie: + # An initial exec load of a local variable, should be relaxed to a + # local-exec access. + adrp c0, :gottprel:w + add c0, c0, :gottprel_lo12:w + ldp x2, x1, [c0] + mrs c0, ctpidr_el0 + add c0, c0, x2 + scbnds c0, c0, x1 + ldr w0, [c0] + ret +load_w1: + # An initial exec load of some external variable, should stay as + # initial exec. + adrp c0, :gottprel:w1 + add c0, c0, :gottprel_lo12:w1 + ldp x2, x1, [c0] + mrs c0, ctpidr_el0 + add c0, c0, x2 + scbnds c0, c0, x1 + ldr w0, [c0] + ret +load_w2: + # A global dynamic load of some external variable. + # Should be relaxed to an initial-exec load, since this is the + # executable and hence we know that this binaries dependencies will be + # available at load time. + mrs c2, ctpidr_el0 + adrp c0, :tlsdesc:w2 + ldr c1, [c0, #:tlsdesc_lo12:w2] + add c0, c0, :tlsdesc_lo12:w2 + nop + .tlsdesccall w2 + blr c1 + ldr w0, [c0] + ret + + .size _start, .-_start diff --git a/ld/testsuite/ld-aarch64/morello-tlsdesc-seen-ie.d b/ld/testsuite/ld-aarch64/morello-tlsdesc-seen-ie.d new file mode 100644 index 0000000000000000000000000000000000000000..fcbd75a7f5fdef0536dc84ecd7c1e706d786a94d --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-tlsdesc-seen-ie.d @@ -0,0 +1,104 @@ +# Checking that: +# 1) TLS sequences are relaxed. +# 2) Relaxed TLS sequences trigger a TPREL128 relocation. +# 3) Relaxed TLS sequences end up referencing that TPREL128 relocation. +# 4) TPREL128 relocation contains a size fragment when the static linker +# knows the size of this variable. +#target: [check_shared_lib_support] +#as: -march=morello+c64 +#ld: -shared +#objdump: -DR -j .got.plt -j .text -j .plt -j .got -j .rodata + + +.*: file format .* + + +Disassembly of section .plt: + +.*<.plt>: +.*: 62bf7bf0 stp c16, c30, [csp, #-32]! +.*: 908...90 adrp c16, .* +.*: c2....11 ldr c17, [c16, #[0-9]+] +.*: 02....10 add c16, c16, #0x[0-9a-f]+ +.*: c2c21220 br c17 +.*: d503201f nop +.*: d503201f nop +.*: d503201f nop + +.*_start@plt: +.*: 908...90 adrp c16, .* +.*: c2....11 ldr c17, [c16, #[0-9]+] +.*: 02....10 add c16, c16, #0x[0-9a-f]+ +.*: c2c21220 br c17 + +.*extf@plt: +.*: 908...90 adrp c16, .* +.*: c2....11 ldr c17, [c16, #[0-9]+] +.*: 02....10 add c16, c16, #0x[0-9a-f]+ +.*: c2c21220 br c17 + +Disassembly of section .text: + +[0-9a-f]+ <IE_function>: +#record: GOT_PAGE + +[0-9a-f]+: 908...80 adrp c0, ([0-9a-f]+) .* +#check: GPAGE string tolower $GOT_PAGE + +[0-9a-f]+: 908...80 adrp c0, GPAGE .* + +[0-9a-f]+: 908...80 adrp c0, GPAGE .* + +.*<f1>: +.*: 97fffff9 bl .* extf@plt +.*: c29bd042 mrs c2, ctpidr_el0 +.*: 908...80 adrp c0, GPAGE .* +#record: VAR1_OFFSET +.*: ........ add c0, c0, #0x([0-9a-f]+) +.*: ........ ldp x0, x1, [c0] +.*: ........ add c0, c2, x0, uxtx +.*: c2c10000 scbnds c0, c0, x1 + +.*<f2>: +.*: 97ffffee bl .* _start@plt +.*: c29bd042 mrs c2, ctpidr_el0 +.*: 908...80 adrp c0, GPAGE .* +#record: VAR2_OFFSET +.*: ........ add c0, c0, #0x([0-9a-f]+) +.*: ........ ldp x0, x1, [c0] +.*: ........ add c0, c2, x0, uxtx +.*: c2c10000 scbnds c0, c0, x1 + +.*<_start>: +.*: c29bd042 mrs c2, ctpidr_el0 +.*: 908...80 adrp c0, GPAGE .* +#record: VAR3_OFFSET +.*: ........ add c0, c0, #0x([0-9a-f]+) +.*: ........ ldp x0, x1, [c0] +.*: ........ add c0, c2, x0, uxtx +.*: c2c10000 scbnds c0, c0, x1 + +Disassembly of section .got: +#check: VAR1_LOC aarch64_page_plus_offset $GOT_PAGE $VAR1_OFFSET +#check: VAR2_LOC aarch64_page_plus_offset $GOT_PAGE $VAR2_OFFSET +#check: VAR3_LOC aarch64_page_plus_offset $GOT_PAGE $VAR3_OFFSET +#check: VAR3_SIZE_LOC format %x [expr "8 + 0x$GOT_PAGE + 0x$VAR3_OFFSET"] + +.* <.got>: + +[0-9a-f]+: .* + ... + +VAR3_LOC: 00000004 udf #4 + VAR3_LOC: R_MORELLO_TPREL128 *ABS*+0x4 + +[0-9a-f]+: 00000000 udf #0 + +VAR3_SIZE_LOC: 00000014 udf #20 + ... + VAR1_LOC: R_MORELLO_TPREL128 var1 + VAR2_LOC: R_MORELLO_TPREL128 var2 + +Disassembly of section .got.plt: + +.* <.*>: + ... + .* + [0-9a-f]+: R_MORELLO_JUMP_SLOT _start + ... + .* + [0-9a-f]+: R_MORELLO_JUMP_SLOT extf + ... diff --git a/ld/testsuite/ld-aarch64/morello-tlsdesc-seen-ie.s b/ld/testsuite/ld-aarch64/morello-tlsdesc-seen-ie.s new file mode 100644 index 0000000000000000000000000000000000000000..3ba0654400f582266ffd978e7ed33c1b17e1b945 --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-tlsdesc-seen-ie.s @@ -0,0 +1,50 @@ +.section .tbss +.globl var2 +var2: + .word 0 + .size var2, .-var2 + +var3: + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .size var3, .-var3 + +.section .text +IE_function: + adrp c0, :gottprel:var1 + adrp c0, :gottprel:var2 + adrp c0, :gottprel:var3 + +f1: + bl extf + mrs c2, CTPIDR_EL0 + adrp c0, :tlsdesc:var1 + ldr c1, [c0, #:tlsdesc_lo12:var1] + add c0, c0, #:tlsdesc_lo12:var1 + nop + .tlsdesccall var1 + blr c1 + +f2: + bl _start + mrs c2, CTPIDR_EL0 + adrp c0, :tlsdesc:var2 + ldr c1, [c0, #:tlsdesc_lo12:var2] + add c0, c0, #:tlsdesc_lo12:var2 + nop + .tlsdesccall var2 + blr c1 + +.globl _start +.type _start, STT_FUNC +_start: + mrs c2, CTPIDR_EL0 + adrp c0, :tlsdesc:var3 + ldr c1, [c0, #:tlsdesc_lo12:var3] + add c0, c0, #:tlsdesc_lo12:var3 + nop + .tlsdesccall var3 + blr c1 diff --git a/ld/testsuite/ld-aarch64/morello-tlsdesc-static.d b/ld/testsuite/ld-aarch64/morello-tlsdesc-static.d index 9026f14115b996ea90628325eb51e1773f08828e..237e6dfdf6f72fe279159ab4e82acbe8c87f3058 100644 --- a/ld/testsuite/ld-aarch64/morello-tlsdesc-static.d +++ b/ld/testsuite/ld-aarch64/morello-tlsdesc-static.d @@ -1,29 +1,74 @@ #source: morello-tlsdesc.s #as: -march=morello+c64 --defsym STATIC=1 #ld: -#objdump: -D -j .got.plt -j .text -j .plt +#objdump: -D -j .got.plt -j .text -j .plt -j .rodata
.*: file format .*
-Disassembly of section .text: - -.*<f2>: -.*: 94000008 bl .* <_start> -.*: c29bd042 mrs c2, ctpidr_el0 -.*: d2a00001 movz x1, #0x0, lsl #16 -.*: d2a00000 movz x0, #0x0, lsl #16 -.*: f2800400 movk x0, #0x20 -.*: f2800081 movk x1, #0x4 -.*: c2a06040 add c0, c2, x0, uxtx -.*: c2c10000 scbnds c0, c0, x1 - -.*<_start>: -.*: c29bd042 mrs c2, ctpidr_el0 -.*: d2a00001 movz x1, #0x0, lsl #16 -.*: d2a00000 movz x0, #0x0, lsl #16 -.*: f2800480 movk x0, #0x24 -.*: f2800281 movk x1, #0x14 -.*: c2a06040 add c0, c2, x0, uxtx -.*: c2c10000 scbnds c0, c0, x1 +Disassembly of section .text: + +[0-9a-f]+ <f2>: + +[0-9a-f]+: c29bd042 mrs c2, ctpidr_el0 +#record: RODATA_PAGE + +[0-9a-f]+: [0-9a-f]+ adrp c0, ([0-9a-f]+) .* +#record: VAR2_OFFSET + +[0-9a-f]+: [0-9a-f]+ add c0, c0, #0x([0-9a-f]+) + +[0-9a-f]+: a9400400 ldp x0, x1, [c0] + +[0-9a-f]+: c2a06040 add c0, c2, x0, uxtx + +[0-9a-f]+: c2c10000 scbnds c0, c0, x1 + +[0-9a-f]+ <access_hidden>: + +[0-9a-f]+: c29bd042 mrs c2, ctpidr_el0 +#check: PAGE string tolower $RODATA_PAGE + +[0-9a-f]+: [0-9a-f]+ adrp c0, PAGE .* +#record: VAR4_OFFSET + +[0-9a-f]+: [0-9a-f]+ add c0, c0, #0x([0-9a-f]+) + +[0-9a-f]+: a9400400 ldp x0, x1, [c0] + +[0-9a-f]+: c2a06040 add c0, c2, x0, uxtx + +[0-9a-f]+: c2c10000 scbnds c0, c0, x1 + +[0-9a-f]+ <access_protected>: + +[0-9a-f]+: c29bd042 mrs c2, ctpidr_el0 +#check: PAGE string tolower $RODATA_PAGE + +[0-9a-f]+: [0-9a-f]+ adrp c0, PAGE .* +#record: VAR5_OFFSET + +[0-9a-f]+: [0-9a-f]+ add c0, c0, #0x([0-9a-f]+) + +[0-9a-f]+: a9400400 ldp x0, x1, [c0] + +[0-9a-f]+: c2a06040 add c0, c2, x0, uxtx + +[0-9a-f]+: c2c10000 scbnds c0, c0, x1 + +[0-9a-f]+ <_start>: + +[0-9a-f]+: c29bd042 mrs c2, ctpidr_el0 +#check: PAGE string tolower $RODATA_PAGE + +[0-9a-f]+: [0-9a-f]+ adrp c0, PAGE .* +#record: VAR3_OFFSET + +[0-9a-f]+: [0-9a-f]+ add c0, c0, #0x([0-9a-f]+) + +[0-9a-f]+: a9400400 ldp x0, x1, [c0] + +[0-9a-f]+: c2a06040 add c0, c2, x0, uxtx + +[0-9a-f]+: c2c10000 scbnds c0, c0, x1 + +Disassembly of section .rodata: + +#check: VAR2_LOC aarch64_page_plus_offset $RODATA_PAGE $VAR2_OFFSET +#check: VAR3_LOC aarch64_page_plus_offset $RODATA_PAGE $VAR3_OFFSET +#check: VAR4_LOC aarch64_page_plus_offset $RODATA_PAGE $VAR4_OFFSET +#check: VAR5_LOC aarch64_page_plus_offset $RODATA_PAGE $VAR5_OFFSET +[0-9a-f]+ <.*>: + +VAR2_LOC: 00000020 udf #32 + +[0-9a-f]+: 00000000 udf #0 + +[0-9a-f]+: 00000004 udf #4 + +[0-9a-f]+: 00000000 udf #0 + +VAR4_LOC: 00000038 udf #56 + +[0-9a-f]+: 00000000 udf #0 + +[0-9a-f]+: 00000004 udf #4 + +[0-9a-f]+: 00000000 udf #0 + +VAR5_LOC: 0000003c udf #60 + +[0-9a-f]+: 00000000 udf #0 + +[0-9a-f]+: 00000004 udf #4 + +[0-9a-f]+: 00000000 udf #0 + +VAR3_LOC: 00000024 udf #36 + +[0-9a-f]+: 00000000 udf #0 + +[0-9a-f]+: 00000014 udf #20 + +[0-9a-f]+: 00000000 udf #0 diff --git a/ld/testsuite/ld-aarch64/morello-tlsdesc-staticpie.d b/ld/testsuite/ld-aarch64/morello-tlsdesc-staticpie.d index bf2b67aa4574db66373a1932acb572609a793d69..b408451f49bde7026773c2b24dae48dafe00309b 100644 --- a/ld/testsuite/ld-aarch64/morello-tlsdesc-staticpie.d +++ b/ld/testsuite/ld-aarch64/morello-tlsdesc-staticpie.d @@ -1,54 +1,78 @@ #source: morello-tlsdesc.s #as: -march=morello+c64 --defsym STATIC=1 #ld: -pie -#objdump: -DR -j .got.plt -j .text -j .plt +#objdump: -DR -j .got.plt -j .text -j .plt -j .rodata
.*: file format .*
-Disassembly of section .plt: - -.*<.plt>: -.*: 62bf7bf0 stp c16, c30, [csp, #-32]! -.*: 908...90 adrp c16, .* -.*: c2....11 ldr c17, [c16, #[0-9]+] -.*: 02....10 add c16, c16, #0x[0-9a-f]+ -.*: c2c21220 br c17 -.*: d503201f nop -.*: d503201f nop -.*: d503201f nop -.*: 62bf8fe2 stp c2, c3, [csp, #-16]! -.*: 908...82 adrp c2, .* -.*: 908...83 adrp c3, .* -.*: c2....42 ldr c2, [c2, #[0-9]+] -.*: 02....63 add c3, c3, #0x[0-9a-f]+ -.*: c2c21040 br c2 -.*: d503201f nop -.*: d503201f nop - -Disassembly of section .text: - -.*<f2>: -.*: 94000008 bl .* <_start> -.*: c29bd042 mrs c2, ctpidr_el0 -.*: d503201f nop -.*: 908...80 adrp c0, .* -.*: c2....01 ldr c1, [c0, #[0-9]+] -.*: 02....00 add c0, c0, #0x[0-9a-f]+ -.*: c2c23020 blr c1 -.*: c2c10000 scbnds c0, c0, x1 - -.*<_start>: -.*: c29bd042 mrs c2, ctpidr_el0 -.*: d2a00001 movz x1, #0x0, lsl #16 -.*: d2a00000 movz x0, #0x0, lsl #16 -.*: f2800480 movk x0, #0x24 -.*: f2800281 movk x1, #0x14 -.*: c2....40 add c0, c2, x0, uxtx -.*: c2c10000 scbnds c0, c0, x1 - -Disassembly of section .got.plt: +Disassembly of section .text: + +[0-9a-f]+ <f2>: + +[0-9a-f]+: c29bd042 mrs c2, ctpidr_el0 +#record: RODATA_PAGE + +[0-9a-f]+: [0-9a-f]+ adrp c0, ([0-9a-f]+) .* +#record: VAR2_OFFSET + +[0-9a-f]+: [0-9a-f]+ add c0, c0, #0x([0-9a-f]+) + +[0-9a-f]+: a9400400 ldp x0, x1, [c0] + +[0-9a-f]+: c2a06040 add c0, c2, x0, uxtx + +[0-9a-f]+: c2c10000 scbnds c0, c0, x1 + +[0-9a-f]+ <access_hidden>: + +[0-9a-f]+: c29bd042 mrs c2, ctpidr_el0 +#check: PAGE string tolower $RODATA_PAGE + +[0-9a-f]+: [0-9a-f]+ adrp c0, PAGE .* +#record: VAR4_OFFSET + +[0-9a-f]+: [0-9a-f]+ add c0, c0, #0x([0-9a-f]+) + +[0-9a-f]+: a9400400 ldp x0, x1, [c0] + +[0-9a-f]+: c2a06040 add c0, c2, x0, uxtx + +[0-9a-f]+: c2c10000 scbnds c0, c0, x1 + +[0-9a-f]+ <access_protected>: + +[0-9a-f]+: c29bd042 mrs c2, ctpidr_el0 +#check: PAGE string tolower $RODATA_PAGE + +[0-9a-f]+: [0-9a-f]+ adrp c0, PAGE .* +#record: VAR5_OFFSET + +[0-9a-f]+: [0-9a-f]+ add c0, c0, #0x([0-9a-f]+) + +[0-9a-f]+: a9400400 ldp x0, x1, [c0] + +[0-9a-f]+: c2a06040 add c0, c2, x0, uxtx + +[0-9a-f]+: c2c10000 scbnds c0, c0, x1 + +[0-9a-f]+ <_start>: + +[0-9a-f]+: c29bd042 mrs c2, ctpidr_el0 +#check: PAGE string tolower $RODATA_PAGE + +[0-9a-f]+: [0-9a-f]+ adrp c0, PAGE .* +#record: VAR3_OFFSET + +[0-9a-f]+: [0-9a-f]+ add c0, c0, #0x([0-9a-f]+) + +[0-9a-f]+: a9400400 ldp x0, x1, [c0] + +[0-9a-f]+: c2a06040 add c0, c2, x0, uxtx + +[0-9a-f]+: c2c10000 scbnds c0, c0, x1 + +Disassembly of section .rodata: + +#check: VAR2_LOC aarch64_page_plus_offset $RODATA_PAGE $VAR2_OFFSET +#check: VAR3_LOC aarch64_page_plus_offset $RODATA_PAGE $VAR3_OFFSET +#check: VAR4_LOC aarch64_page_plus_offset $RODATA_PAGE $VAR4_OFFSET +#check: VAR5_LOC aarch64_page_plus_offset $RODATA_PAGE $VAR5_OFFSET +[0-9a-f]+ <.*>: + +VAR2_LOC: 00000020 udf #32 + +[0-9a-f]+: 00000000 udf #0 + +[0-9a-f]+: 00000004 udf #4 + +[0-9a-f]+: 00000000 udf #0 + +VAR4_LOC: 00000038 udf #56 + +[0-9a-f]+: 00000000 udf #0 + +[0-9a-f]+: 00000004 udf #4 + +[0-9a-f]+: 00000000 udf #0 + +VAR5_LOC: 0000003c udf #60 + +[0-9a-f]+: 00000000 udf #0 + +[0-9a-f]+: 00000004 udf #4 + +[0-9a-f]+: 00000000 udf #0 + +VAR3_LOC: 00000024 udf #36 + +[0-9a-f]+: 00000000 udf #0 + +[0-9a-f]+: 00000014 udf #20 + +[0-9a-f]+: 00000000 udf #0 + +Disassembly of section .got.plt:
.*: - ... - .*: R_MORELLO_TLSDESC *ABS* + ... diff --git a/ld/testsuite/ld-aarch64/morello-tlsdesc.d b/ld/testsuite/ld-aarch64/morello-tlsdesc.d index 58336a7cbc8f3641d35ad3d50b397fe17c6948b1..0dc3cbb430c7c2fd89a89d6b58a6998bb0595eaa 100644 --- a/ld/testsuite/ld-aarch64/morello-tlsdesc.d +++ b/ld/testsuite/ld-aarch64/morello-tlsdesc.d @@ -1,4 +1,11 @@ +# Checking that: +# 1) TLS sequences are not relaxed. +# 2) TLS sequences trigger a TLSDESC relocation. +# 3) TLS sequences end up referencing that TLSDESC relocation. +# 4) TLSDESC relocation contains a size fragment when the static linker +# knows the size of this variable. #source: morello-tlsdesc.s +#target: [check_shared_lib_support] #as: -march=morello+c64 #ld: -shared #objdump: -DR -j .got.plt -j .text -j .plt @@ -19,12 +26,6 @@ Disassembly of section .plt: .*: d503201f nop .*: d503201f nop
-.*_start@plt: -.*: 908...90 adrp c16, .* -.*: c2....11 ldr c17, [c16, #[0-9]+] -.*: 02....10 add c16, c16, #0x[0-9a-f]+ -.*: c2c21220 br c17 - .*extf@plt: .*: 908...90 adrp c16, .* .*: c2....11 ldr c17, [c16, #[0-9]+] @@ -48,42 +49,79 @@ Disassembly of section .text: .*<f1>: .*: 97fffff4 bl .* extf@plt .*: c29bd042 mrs c2, ctpidr_el0 +#record: GOTPLT_PAGE +.*: 908...80 adrp c0, ([0-9a-f]+) .* +#record: VAR1_OFFSET +.*: c2....01 ldr c1, [c0, #([0-9]+)] +#check: VAR1_HEX format %x $VAR1_OFFSET +.*: 02....00 add c0, c0, #0xVAR1_HEX .*: d503201f nop -.*: 908...80 adrp c0, .* -.*: c2....01 ldr c1, [c0, #[0-9]+] -.*: 02....00 add c0, c0, #0x[0-9a-f]+ .*: c2c23020 blr c1 -.*: c2c10000 scbnds c0, c0, x1
+#check: GPAGE string tolower $GOTPLT_PAGE .*<f2>: -.*: 97ffffe8 bl .* _start@plt .*: c29bd042 mrs c2, ctpidr_el0 +.*: 908...80 adrp c0, GPAGE .* +#record: VAR2_OFFSET +.*: c2....01 ldr c1, [c0, #([0-9]+)] +#check: VAR2_HEX format %x $VAR2_OFFSET +.*: 02....00 add c0, c0, #0xVAR2_HEX +.*: d503201f nop +.*: c2c23020 blr c1 + +.*<access_hidden>: +.*: c29bd042 mrs c2, ctpidr_el0 +.*: 908...80 adrp c0, GPAGE .* +#record: VAR4_OFFSET +.*: c2....01 ldr c1, [c0, #([0-9]+)] +#check: VAR4_HEX format %x $VAR4_OFFSET +.*: 02....00 add c0, c0, #0xVAR4_HEX +.*: d503201f nop +.*: c2c23020 blr c1 + +.*<access_protected>: +.*: c29bd042 mrs c2, ctpidr_el0 +.*: 908...80 adrp c0, GPAGE .* +#record: VAR5_OFFSET +.*: c2....01 ldr c1, [c0, #([0-9]+)] +#check: VAR5_HEX format %x $VAR5_OFFSET +.*: 02....00 add c0, c0, #0xVAR5_HEX .*: d503201f nop -.*: 908...80 adrp c0, .* -.*: c2....01 ldr c1, [c0, #[0-9]+] -.*: 02....00 add c0, c0, #0x[0-9a-f]+ .*: c2c23020 blr c1 -.*: c2c10000 scbnds c0, c0, x1
.*<_start>: .*: c29bd042 mrs c2, ctpidr_el0 +.*: 908...80 adrp c0, GPAGE .* +#record: VAR3_OFFSET +.*: c2....01 ldr c1, [c0, #([0-9]+)] +#check: VAR3_HEX format %x $VAR3_OFFSET +.*: 02....00 add c0, c0, #0xVAR3_HEX .*: d503201f nop -.*: 908...80 adrp c0, .* -.*: c2....01 ldr c1, [c0, #[0-9]+] -.*: 02....00 add c0, c0, #0x[0-9a-f]+ .*: c2c23020 blr c1 -.*: c2c10000 scbnds c0, c0, x1
Disassembly of section .got.plt: +#check: VAR1_LOC aarch64_page_plus_offset $GOTPLT_PAGE [format %x $VAR1_OFFSET] +#check: VAR2_LOC aarch64_page_plus_offset $GOTPLT_PAGE [format %x $VAR2_OFFSET] +#check: VAR3_LOC aarch64_page_plus_offset $GOTPLT_PAGE [format %x $VAR3_OFFSET] +#check: VAR4_LOC aarch64_page_plus_offset $GOTPLT_PAGE [format %x $VAR4_OFFSET] +#check: VAR5_LOC aarch64_page_plus_offset $GOTPLT_PAGE [format %x $VAR5_OFFSET] +#check: VAR3_SIZE_LOC format %x [expr "24 + 0x$GOTPLT_PAGE + $VAR3_OFFSET"] +#check: VAR4_SIZE_LOC format %x [expr "24 + 0x$GOTPLT_PAGE + $VAR4_OFFSET"] +#check: VAR5_SIZE_LOC format %x [expr "24 + 0x$GOTPLT_PAGE + $VAR5_OFFSET"]
.*: - ... -.*: [0-9a-f]+ .* - .*: R_MORELLO_JUMP_SLOT _start - ... + ... .*: [0-9a-f]+ .* .*: R_MORELLO_JUMP_SLOT extf - ... - .*: R_MORELLO_TLSDESC *ABS*+0x4 - .*: R_MORELLO_TLSDESC var1 - .*: R_MORELLO_TLSDESC var2 + ... + VAR3_LOC: R_MORELLO_TLSDESC *ABS*+0x4 + +VAR3_SIZE_LOC: 00000014 .* + ... + VAR5_LOC: R_MORELLO_TLSDESC var5 + +VAR5_SIZE_LOC: 00000004 .* + ... + VAR1_LOC: R_MORELLO_TLSDESC var1 + VAR4_LOC: R_MORELLO_TLSDESC *ABS*+0x18 + +VAR4_SIZE_LOC: 00000004 .* + ... + VAR2_LOC: R_MORELLO_TLSDESC var2 diff --git a/ld/testsuite/ld-aarch64/morello-tlsdesc.s b/ld/testsuite/ld-aarch64/morello-tlsdesc.s index 5eab58a059df1879dad41cda94023acb3a4e92fc..33eeceb2f160e076a4cdd210817ea3a0fd979228 100644 --- a/ld/testsuite/ld-aarch64/morello-tlsdesc.s +++ b/ld/testsuite/ld-aarch64/morello-tlsdesc.s @@ -1,5 +1,9 @@ .section .tbss .globl var2 +.globl var4 +.hidden var4 +.globl var5 +.protected var5 var2: .word 0 .size var2, .-var2 @@ -11,40 +15,60 @@ var3: .word 0 .word 0 .size var3, .-var3 +var4: + .word 0 + .size var4, .-var4 +var5: + .word 0 + .size var5, .-var5
.section .text .ifndef STATIC f1: bl extf mrs c2, CTPIDR_EL0 - nop adrp c0, :tlsdesc:var1 ldr c1, [c0, #:tlsdesc_lo12:var1] add c0, c0, #:tlsdesc_lo12:var1 + nop .tlsdesccall var1 blr c1 - scbnds c0, c0, x1 .endif
f2: - bl _start mrs c2, CTPIDR_EL0 - nop adrp c0, :tlsdesc:var2 ldr c1, [c0, #:tlsdesc_lo12:var2] add c0, c0, #:tlsdesc_lo12:var2 + nop + .tlsdesccall var2 + blr c1 + +access_hidden: + mrs c2, CTPIDR_EL0 + adrp c0, :tlsdesc:var4 + ldr c1, [c0, #:tlsdesc_lo12:var4] + add c0, c0, #:tlsdesc_lo12:var4 + nop + .tlsdesccall var2 + blr c1 + +access_protected: + mrs c2, CTPIDR_EL0 + adrp c0, :tlsdesc:var5 + ldr c1, [c0, #:tlsdesc_lo12:var5] + add c0, c0, #:tlsdesc_lo12:var5 + nop .tlsdesccall var2 blr c1 - scbnds c0, c0, x1
.globl _start .type _start, STT_FUNC _start: mrs c2, CTPIDR_EL0 - nop adrp c0, :tlsdesc:var3 ldr c1, [c0, #:tlsdesc_lo12:var3] add c0, c0, #:tlsdesc_lo12:var3 + nop .tlsdesccall var3 blr c1 - scbnds c0, c0, x1 diff --git a/ld/testsuite/ld-aarch64/morello-tlsie-overflow.d b/ld/testsuite/ld-aarch64/morello-tlsie-overflow.d new file mode 100644 index 0000000000000000000000000000000000000000..5963531c5ed58743b68909cc6046d8d76463a1dd --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-tlsie-overflow.d @@ -0,0 +1,4 @@ +#as: -march=morello+c64 +#ld: tmpdir/tls-shared.so +#error: .*: in function `_start': +#error: .*: relocation truncated to fit: R_MORELLO_TLSIE_ADR_GOTTPREL_PAGE20 against symbol `w1' defined in .tbss section .* diff --git a/ld/testsuite/ld-aarch64/morello-tlsie-overflow.s b/ld/testsuite/ld-aarch64/morello-tlsie-overflow.s new file mode 100644 index 0000000000000000000000000000000000000000..cf6d14bdb01771edd7e1253458eb96f312066d24 --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-tlsie-overflow.s @@ -0,0 +1,16 @@ + .text + + .align 2 + .p2align 4,,11 + .global _start + .type _start,%function +_start: + adrp c2, :gottprel:w1 + add c2, c2, :gottprel_lo12:w1 + ldp x2, x1, [c2] + # Add some padding in the text section to ensure that the GOT section + # is too far away for the gottprel relocation above. Out of interest, + # we can't add this padding in the .got section since the order of the + # link determines that the GOT we add for relocations will be before + # the GOT added in the file. + .zero 0x80000000 diff --git a/ld/testsuite/ld-aarch64/morello-tlsie-pie.d b/ld/testsuite/ld-aarch64/morello-tlsie-pie.d new file mode 100644 index 0000000000000000000000000000000000000000..65b2c349a869353ff9315c49aa321d4b8edb61b4 --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-tlsie-pie.d @@ -0,0 +1,72 @@ +# Checking the following: +# Relaxations have occured. +# .rodata stubs have been emitted. +# Values are correct. +# Include some other data in .rodata in order to check we offset correctly. +# +# Also check the behavior on a global and local symbol (just in case). +#source: morello-tlsie.s +#as: -march=morello+c64 +#ld: -pie +#objdump: -Dr -j .rodata -j .text + +.*: +file format .* + + +Disassembly of section .text: + +[0-9a-f]+ <_start>: +#record: RODATA_PAGE + +[0-9a-f]+: [0-9a-f]+ adrp c2, ([0-9a-f]+) .* +#record: STUB1_OFFSET + +[0-9a-f]+: [0-9a-f]+ add c2, c2, #0x([0-9a-f]+) + +[0-9a-f]+: a9400442 ldp x2, x1, [c2] +#check: PAGE string tolower $RODATA_PAGE + +[0-9a-f]+: [0-9a-f]+ adrp c2, PAGE .* +#record: STUB2_OFFSET + +[0-9a-f]+: [0-9a-f]+ add c2, c2, #0x([0-9a-f]+) + +[0-9a-f]+: a9400442 ldp x2, x1, [c2] + +[0-9a-f]+: [0-9a-f]+ adrp c2, PAGE .* +#record: STUB3_OFFSET + +[0-9a-f]+: [0-9a-f]+ add c2, c2, #0x([0-9a-f]+) + +[0-9a-f]+: a9400442 ldp x2, x1, [c2] + +[0-9a-f]+: [0-9a-f]+ adrp c2, PAGE .* +#record: STUB4_OFFSET + +[0-9a-f]+: [0-9a-f]+ add c2, c2, #0x([0-9a-f]+) + +[0-9a-f]+: a9400442 ldp x2, x1, [c2] + +Disassembly of section .rodata: + +[0-9a-f]+ <.*>: + +[0-9a-f]+: 6c6c6548 ldnp d8, d25, [x10, #-320] + +[0-9a-f]+: 6f77206f umlal2 v15.4s, v3.8h, v7.h[3] + +[0-9a-f]+: 0a646c72 bic w18, w3, w4, lsr #27 + +[0-9a-f]+: 00000000 udf #0 +#check: STUB1_LOC aarch64_page_plus_offset $RODATA_PAGE $STUB1_OFFSET +#check: HEX_OFF1 format %08x [expr "65540 + 32"] +#check: HEX_SIZE1 format %08x 65592 + +STUB1_LOC: HEX_OFF1 .* + +[0-9a-f]+: 00000000 udf #0 + +[0-9a-f]+: HEX_SIZE1 .* + +[0-9a-f]+: 00000000 udf #0 +#check: STUB2_LOC aarch64_page_plus_offset $RODATA_PAGE $STUB2_OFFSET +#check: HEX_OFF2 format %08x [expr "65540 + 32 + 65592"] +#check: HEX_SIZE2 format %08x 100 + +STUB2_LOC: HEX_OFF2 .* + +[0-9a-f]+: 00000000 udf #0 + +[0-9a-f]+: HEX_SIZE2 .* + +[0-9a-f]+: 00000000 udf #0 +#check: STUB3_LOC aarch64_page_plus_offset $RODATA_PAGE $STUB3_OFFSET +#check: HEX_OFF3 format %08x [expr "65540 + 32 + 65592 + 100"] +#check: HEX_SIZE3 format %08x 10 + +STUB3_LOC: HEX_OFF3 .* + +[0-9a-f]+: 00000000 udf #0 + +[0-9a-f]+: HEX_SIZE3 .* + +[0-9a-f]+: 00000000 udf #0 +#check: STUB4_LOC aarch64_page_plus_offset $RODATA_PAGE $STUB4_OFFSET +#check: HEX_OFF4 format %08x [expr "65540 + 32 + 65592 + 100 + 10"] +#check: HEX_SIZE4 format %08x 15 + +STUB4_LOC: HEX_OFF4 .* + +[0-9a-f]+: 00000000 udf #0 + +[0-9a-f]+: HEX_SIZE4 .* + +[0-9a-f]+: 00000000 udf #0 diff --git a/ld/testsuite/ld-aarch64/morello-tlsie-shared.d b/ld/testsuite/ld-aarch64/morello-tlsie-shared.d new file mode 100644 index 0000000000000000000000000000000000000000..cb569c71c6eae47f58bde51ae4f43a4074fad919 --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-tlsie-shared.d @@ -0,0 +1,84 @@ +# Checking the following: +# Relaxations have not occured. +# Values point to the GOT. +# Fragment in GOT contains size hint if known. +# Fragment in GOT does not contain any offset (except for the relocation +# against a local symbol where the fragment is populated in order to give +# the dynamic loader a base to use). +# +# Check the disassembly of rodata just to demonstrate we haven't emitted the +# TLS data stubs for an IE -> LE relaxation. +# +# Also check the behavior on a global and local symbol to check the behaviour +# of a local symbol. +#source: morello-tlsie.s +#target: [check_shared_lib_support] +#as: -march=morello+c64 +#ld: -shared +#objdump: -DR -j .rodata -j .text -j .got + +.*: +file format .* + + +Disassembly of section .text: + +[0-9a-f]+ <_start>: +#record: GOT_PAGE + +[0-9a-f]+: [0-9a-f]+ adrp c2, ([0-9a-f]+) .* +#record: VAR1_OFFSET + +[0-9a-f]+: [0-9a-f]+ add c2, c2, #0x([0-9a-f]+) + +[0-9a-f]+: a9400442 ldp x2, x1, [c2] +#check: PAGE string tolower $GOT_PAGE + +[0-9a-f]+: [0-9a-f]+ adrp c2, PAGE .* +#record: VAR2_OFFSET + +[0-9a-f]+: [0-9a-f]+ add c2, c2, #0x([0-9a-f]+) + +[0-9a-f]+: a9400442 ldp x2, x1, [c2] + +[0-9a-f]+: [0-9a-f]+ adrp c2, PAGE .* +#record: VAR3_OFFSET + +[0-9a-f]+: [0-9a-f]+ add c2, c2, #0x([0-9a-f]+) + +[0-9a-f]+: a9400442 ldp x2, x1, [c2] + +[0-9a-f]+: [0-9a-f]+ adrp c2, PAGE .* +#record: VAR4_OFFSET + +[0-9a-f]+: [0-9a-f]+ add c2, c2, #0x([0-9a-f]+) + +[0-9a-f]+: a9400442 ldp x2, x1, [c2] + +Disassembly of section .rodata: + +# This is just the "Hello world\n" we put there to cause some interference with +# the .rodata section we create for the static tests. +[0-9a-f]+ <.*>: + +[0-9a-f]+: 6c6c6548 ldnp d8, d25, [x10, #-320] + +[0-9a-f]+: 6f77206f umlal2 v15.4s, v3.8h, v7.h[3] + +[0-9a-f]+: 0a646c72 bic w18, w3, w4, lsr #27 + ... + +Disassembly of section .got: + +[0-9a-f]+ <.got>: + +[0-9a-f]+: .* + ... +#check: VAR4_LOC aarch64_page_plus_offset $GOT_PAGE $VAR4_OFFSET +#check: VAR3_LOC aarch64_page_plus_offset $GOT_PAGE $VAR3_OFFSET +#check: VAR2_LOC aarch64_page_plus_offset $GOT_PAGE $VAR2_OFFSET +#check: VAR1_LOC aarch64_page_plus_offset $GOT_PAGE $VAR1_OFFSET +#check: VAR4_TLS_OFFSET format %08x [expr "65592 + 65540 + 100 + 10"] +#check: VAR4_TLS_OFF format %x [expr "65592 + 65540 + 100 + 10"] +#check: VAR3_TLS_OFFSET format %08x [expr "65592 + 65540 + 100"] +#check: VAR3_TLS_OFF format %x [expr "65592 + 65540 + 100"] +#check: VAR2_TLS_OFFSET format %08x [expr "65592 + 65540"] +#check: VAR2_TLS_OFF format %x [expr "65592 + 65540"] + +VAR2_LOC: VAR2_TLS_OFFSET .* + VAR2_LOC: R_MORELLO_TPREL128 *ABS*+0xVAR2_TLS_OFF + +[0-9a-f]+: 00000000 .* + +[0-9a-f]+: 00000064 .* + +[0-9a-f]+: 00000000 .* + +VAR3_LOC: VAR3_TLS_OFFSET .* + VAR3_LOC: R_MORELLO_TPREL128 *ABS*+0xVAR3_TLS_OFF + +[0-9a-f]+: 00000000 .* + +[0-9a-f]+: 0000000a .* + ... + VAR4_LOC: R_MORELLO_TPREL128 y + +[0-9a-f]+: 0000000f .* + ... + VAR1_LOC: R_MORELLO_TPREL128 a + diff --git a/ld/testsuite/ld-aarch64/morello-tlsie.d b/ld/testsuite/ld-aarch64/morello-tlsie.d new file mode 100644 index 0000000000000000000000000000000000000000..ae4648b85edd042da7610d7e6402c15dd1e73fcd --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-tlsie.d @@ -0,0 +1,71 @@ +# Checking the following: +# Relaxations have occured. +# .rodata stubs have been emitted. +# Values are correct. +# Include some other data in .rodata in order to check we offset correctly. +# +# Also check the behavior on a global and local symbol (just in case). +#as: -march=morello+c64 +#ld: -static +#objdump: -Dr -j .rodata -j .text + +.*: +file format .* + + +Disassembly of section .text: + +[0-9a-f]+ <_start>: +#record: RODATA_PAGE + +[0-9a-f]+: [0-9a-f]+ adrp c2, ([0-9a-f]+) .* +#record: STUB1_OFFSET + +[0-9a-f]+: [0-9a-f]+ add c2, c2, #0x([0-9a-f]+) + +[0-9a-f]+: a9400442 ldp x2, x1, [c2] +#check: PAGE string tolower $RODATA_PAGE + +[0-9a-f]+: [0-9a-f]+ adrp c2, PAGE .* +#record: STUB2_OFFSET + +[0-9a-f]+: [0-9a-f]+ add c2, c2, #0x([0-9a-f]+) + +[0-9a-f]+: a9400442 ldp x2, x1, [c2] + +[0-9a-f]+: [0-9a-f]+ adrp c2, PAGE .* +#record: STUB3_OFFSET + +[0-9a-f]+: [0-9a-f]+ add c2, c2, #0x([0-9a-f]+) + +[0-9a-f]+: a9400442 ldp x2, x1, [c2] + +[0-9a-f]+: [0-9a-f]+ adrp c2, PAGE .* +#record: STUB4_OFFSET + +[0-9a-f]+: [0-9a-f]+ add c2, c2, #0x([0-9a-f]+) + +[0-9a-f]+: a9400442 ldp x2, x1, [c2] + +Disassembly of section .rodata: + +[0-9a-f]+ <.*>: + +[0-9a-f]+: 6c6c6548 ldnp d8, d25, [x10, #-320] + +[0-9a-f]+: 6f77206f umlal2 v15.4s, v3.8h, v7.h[3] + +[0-9a-f]+: 0a646c72 bic w18, w3, w4, lsr #27 + +[0-9a-f]+: 00000000 udf #0 +#check: STUB1_LOC aarch64_page_plus_offset $RODATA_PAGE $STUB1_OFFSET +#check: HEX_OFF1 format %08x [expr "65540 + 32"] +#check: HEX_SIZE1 format %08x 65592 + +STUB1_LOC: HEX_OFF1 .* + +[0-9a-f]+: 00000000 udf #0 + +[0-9a-f]+: HEX_SIZE1 .* + +[0-9a-f]+: 00000000 udf #0 +#check: STUB2_LOC aarch64_page_plus_offset $RODATA_PAGE $STUB2_OFFSET +#check: HEX_OFF2 format %08x [expr "65540 + 32 + 65592"] +#check: HEX_SIZE2 format %08x 100 + +STUB2_LOC: HEX_OFF2 .* + +[0-9a-f]+: 00000000 udf #0 + +[0-9a-f]+: HEX_SIZE2 .* + +[0-9a-f]+: 00000000 udf #0 +#check: STUB3_LOC aarch64_page_plus_offset $RODATA_PAGE $STUB3_OFFSET +#check: HEX_OFF3 format %08x [expr "65540 + 32 + 65592 + 100"] +#check: HEX_SIZE3 format %08x 10 + +STUB3_LOC: HEX_OFF3 .* + +[0-9a-f]+: 00000000 udf #0 + +[0-9a-f]+: HEX_SIZE3 .* + +[0-9a-f]+: 00000000 udf #0 +#check: STUB4_LOC aarch64_page_plus_offset $RODATA_PAGE $STUB4_OFFSET +#check: HEX_OFF4 format %08x [expr "65540 + 32 + 65592 + 100 + 10"] +#check: HEX_SIZE4 format %08x 15 + +STUB4_LOC: HEX_OFF4 .* + +[0-9a-f]+: 00000000 udf #0 + +[0-9a-f]+: HEX_SIZE4 .* + +[0-9a-f]+: 00000000 udf #0 diff --git a/ld/testsuite/ld-aarch64/morello-tlsie.s b/ld/testsuite/ld-aarch64/morello-tlsie.s new file mode 100644 index 0000000000000000000000000000000000000000..6f2688bae03a69141a0f44147ba369c3037c64fc --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-tlsie.s @@ -0,0 +1,50 @@ + .global p + .global a + .global x + .hidden x + .global y + .protected y + .section .tbss,"awT",%nobits +p: + .zero 65540 +a: + .zero 65540 + .zero 52 + .size a,65592 +b: + .zero 100 + .size b,100 +x: + .zero 10 + .size x, 10 +y: + .zero 15 + .size y, 15 + + .section .rodata + .string "Hello world\n" + .text + +# Compute the address of an integer within structure a, padded +# by an array of size 48 + + .align 2 + .p2align 4,,11 + .global _start + .type _start,%function +_start: + adrp c2, :gottprel:a + add c2, c2, :gottprel_lo12:a + ldp x2, x1, [c2] + + adrp c2, :gottprel:b + add c2, c2, :gottprel_lo12:b + ldp x2, x1, [c2] + + adrp c2, :gottprel:x + add c2, c2, :gottprel_lo12:x + ldp x2, x1, [c2] + + adrp c2, :gottprel:y + add c2, c2, :gottprel_lo12:y + ldp x2, x1, [c2] diff --git a/ld/testsuite/ld-aarch64/morello-tlsle-pie.d b/ld/testsuite/ld-aarch64/morello-tlsle-pie.d new file mode 100644 index 0000000000000000000000000000000000000000..736bcd44ecee23f174f07afbc6c5372eeaa67078 --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-tlsle-pie.d @@ -0,0 +1,33 @@ +# Checking the following: +# tprel relocations have provided the offset. +# tprel relocations account for the TCB (i.e. 32 extra bytes on top of the +# size of `p` added to the thread pointer in order to get to `a`). +# +# size relocations have given us the size. +# +# Also check the behaviour on a global and local symbol (just in case). +#source: morello-tlsle.s +#as: -march=morello+c64 +#ld: -pie +#objdump: -dr + +.*: +file format .* + + +Disassembly of section .text: + +[0-9a-f]+ <_start>: + +[0-9a-f]+: d2a00022 mov x2, #0x10000 // #65536 + +[0-9a-f]+: f2800482 movk x2, #0x24 + +[0-9a-f]+: d2a00021 mov x1, #0x10000 // #65536 + +[0-9a-f]+: f2800701 movk x1, #0x38 + +[0-9a-f]+: d2a00042 mov x2, #0x20000 // #131072 + +[0-9a-f]+: f2800b82 movk x2, #0x5c + +[0-9a-f]+: d2a00001 movz x1, #0x0, lsl #16 + +[0-9a-f]+: f2800c81 movk x1, #0x64 + +[0-9a-f]+: c29bd040 mrs c0, ctpidr_el0 + +[0-9a-f]+: c2a26000 add c0, c0, x2, uxtx + +[0-9a-f]+: c2c10000 scbnds c0, c0, x1 + +[0-9a-f]+: b9400000 ldr w0, [c0] + +[0-9a-f]+: c2c253c0 ret c30 + diff --git a/ld/testsuite/ld-aarch64/morello-tlsle.d b/ld/testsuite/ld-aarch64/morello-tlsle.d new file mode 100644 index 0000000000000000000000000000000000000000..651816ebc7e3e321f4c1f5dd78c2c5b4517998f3 --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-tlsle.d @@ -0,0 +1,31 @@ +# Checking the following: +# tprel relocations have provided the offset. +# tprel relocations account for the TCB (i.e. 32 extra bytes on top of the +# size of `p` added to the thread pointer in order to get to `a`). +# +# size relocations have given us the size. +# +# Also check the behaviour on a global and local symbol (just in case). +#as: -march=morello+c64 +#ld: -static +#objdump: -dr + +.*: +file format .* + + +Disassembly of section .text: + +[0-9a-f]+ <_start>: + +[0-9a-f]+: d2a00022 mov x2, #0x10000 // #65536 + +[0-9a-f]+: f2800482 movk x2, #0x24 + +[0-9a-f]+: d2a00021 mov x1, #0x10000 // #65536 + +[0-9a-f]+: f2800701 movk x1, #0x38 + +[0-9a-f]+: d2a00042 mov x2, #0x20000 // #131072 + +[0-9a-f]+: f2800b82 movk x2, #0x5c + +[0-9a-f]+: d2a00001 movz x1, #0x0, lsl #16 + +[0-9a-f]+: f2800c81 movk x1, #0x64 + +[0-9a-f]+: c29bd040 mrs c0, ctpidr_el0 + +[0-9a-f]+: c2a26000 add c0, c0, x2, uxtx + +[0-9a-f]+: c2c10000 scbnds c0, c0, x1 + +[0-9a-f]+: b9400000 ldr w0, [c0] + +[0-9a-f]+: c2c253c0 ret c30 diff --git a/ld/testsuite/ld-aarch64/morello-tlsle.s b/ld/testsuite/ld-aarch64/morello-tlsle.s new file mode 100644 index 0000000000000000000000000000000000000000..1cd65a49c38c059705363d0020b87fae49f68214 --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-tlsle.s @@ -0,0 +1,37 @@ + .global p + .global a + .section .tbss,"awT",%nobits +p: + .zero 65540 +a: + .zero 65540 + .zero 52 + .size a,65592 +b: + .zero 100 + .size b,100 + .text + +# Compute the address of an integer within structure a, padded +# by an array of size 48 + + .align 2 + .p2align 4,,11 + .global _start + .type _start,%function +_start: + movz x2, #:tprel_g1:a + movk x2, #:tprel_g0_nc:a + movz x1, #:size_g1:a + movk x1, #:size_g0_nc:a + + movz x2, #:tprel_g1:b + movk x2, #:tprel_g0_nc:b + movz x1, #:size_g1:b + movk x1, #:size_g0_nc:b + + mrs c0, ctpidr_el0 + add c0, c0, x2 + scbnds c0, c0, x1 + ldr w0, [c0] + ret diff --git a/ld/testsuite/ld-aarch64/tls-shared.s b/ld/testsuite/ld-aarch64/tls-shared.s new file mode 100644 index 0000000000000000000000000000000000000000..9962e755cc70584b3266b5e920667ef8677a3fe6 --- /dev/null +++ b/ld/testsuite/ld-aarch64/tls-shared.s @@ -0,0 +1,20 @@ + .text + .global w1 + .global w2 + .global w3 + .section .tbss,"awT",@nobits + .align 2 + .type w1, %object + .size w1, 4 +w1: + .zero 4 + + .type w2, %object + .size w2, 4 +w2: + .zero 4 + + .type w3, %object + .size w3, 4 +w3: + .zero 4 diff --git a/ld/testsuite/ld-aarch64/tlsle-symbol-offset.d b/ld/testsuite/ld-aarch64/tlsle-symbol-offset.d index f1c6abf911e2730a36f3ffa1792843575d4d5a5b..41aec5bac7a873f850fd352ceb938f47b06453b0 100644 --- a/ld/testsuite/ld-aarch64/tlsle-symbol-offset.d +++ b/ld/testsuite/ld-aarch64/tlsle-symbol-offset.d @@ -1,6 +1,6 @@ #source: tlsle-symbol-offset.s #target: [check_shared_lib_support] -#ld: -shared -T relocs.ld -e0 +#ld: -T relocs.ld -e0 #objdump: -dr #... Disassembly of section .text: