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morello-binutils: Only check for valid Morello bounds on non-exec syms

by Matthew Malcomson

Capabilities pointing to symbols in SEC_CODE sections are given the bounds of the entire PCC. We ensure that the PCC bounds are padded and aligned as needed in the linker. Capabilities pointing to other symbols (e.g. in data sections) are given the bounds of the symbol that they point to. It is the responsibility of the assembly generator (i.e. usually the compiler) to ensure these bounds are correctly aligned and padded as necessary. We emit a warning for imprecise bounds in the second case, until this patch that warning also looked at the first case. This was a mistake and is rectified in this commit. ############### Attachment also inlined for ease of reply ############### diff --git a/bfd/elfnn-aarch64.c b/bfd/elfnn-aarch64.c index 3e0562b72bc69a9c43f01c80c604b85c582f4f7b..da3c629fcdbfbceed633d9af7c5751dd358492fc 100644 --- a/bfd/elfnn-aarch64.c +++ b/bfd/elfnn-aarch64.c @@ -6965,17 +6965,6 @@ c64_fixup_frag (bfd *input_bfd, struct bfd_link_info *info, bfd_vma base = value, limit = value + size; unsigned align = 0; - if (!bounds_ok && !c64_valid_cap_range (&base, &limit, &align)) - { - /* Just warn about this. It's not a requirement that bounds on - objects should be precise, so there's no reason to error out on - such an object. */ - /* xgettext:c-format */ - _bfd_error_handler - (_("%pB: capability range for '%s' may exceed object bounds"), - input_bfd, sym_name); - } - if (perm_sec && perm_sec->flags & SEC_CODE) { /* Any symbol pointing into an executable section gets bounds according @@ -6994,6 +6983,16 @@ c64_fixup_frag (bfd *input_bfd, struct bfd_link_info *info, data or jump to other functions. */ size = pcc_high - pcc_low; } + else if (!bounds_ok && !c64_valid_cap_range (&base, &limit, &align)) + { + /* Just warn about this. It's not a requirement that bounds on + objects should be precise, so there's no reason to error out on + such an object. */ + /* xgettext:c-format */ + _bfd_error_handler + (_("%pB: capability range for '%s' may exceed object bounds"), + input_bfd, sym_name); + } if (perm_sec != NULL) { diff --git a/ld/testsuite/ld-aarch64/aarch64-elf.exp b/ld/testsuite/ld-aarch64/aarch64-elf.exp index 4200c1d17e97ac9b54f2a0a051f15f0d51d47c06..a07a6c50bb8b601761cf38607afbc0a4dcc9ef0c 100644 --- a/ld/testsuite/ld-aarch64/aarch64-elf.exp +++ b/ld/testsuite/ld-aarch64/aarch64-elf.exp @@ -390,6 +390,8 @@ run_dump_test_lp64 "morello-illegal-tls" run_dump_test_lp64 "morello-illegal-tls-pie" run_dump_test_lp64 "morello-illegal-tls-shared" +run_dump_test_lp64 "morello-large-function" + run_dump_test "no-morello-syms-static" run_dump_test "reloc-overflow-bad" diff --git a/ld/testsuite/ld-aarch64/morello-large-function.d b/ld/testsuite/ld-aarch64/morello-large-function.d new file mode 100644 index 0000000000000000000000000000000000000000..dc0af92e12f9ab7203a400997ded14c8bdf4172c --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-large-function.d @@ -0,0 +1,23 @@ +# Mainly here to check that this actually links. +# This testcase used to complain that the function capability may have +# imprecise bounds, but since such capabilities are given PCC bounds that error +# was invalid. +# +# Even though the only point is to check that the testcase links, we still +# ensure that the dump of the .data section contains a relocation with the +# correct permissions. +#as: -march=morello+c64 +#ld: -pie -static +#objdump: -DR -j .data + +.*: file format .* + + +Disassembly of section \.data: + +[0-9a-f]+ <__data_start>: + *[0-9a-f]+: .* + .*: R_MORELLO_RELATIVE \*ABS\*\+.* + *[0-9a-f]+: .* udf #0 + *[0-9a-f]+: .* + *[0-9a-f]+: 04000000 .* diff --git a/ld/testsuite/ld-aarch64/morello-large-function.s b/ld/testsuite/ld-aarch64/morello-large-function.s new file mode 100644 index 0000000000000000000000000000000000000000..46cb51e0c68cba982e8bf2b83b696399a6225f21 --- /dev/null +++ b/ld/testsuite/ld-aarch64/morello-large-function.s @@ -0,0 +1,9 @@ +.data + .chericap _start +.text + .globl _start + .type _start,@function +_start: + ret + .zero 0x8000 + .size _start, .-_start

1 year, 6 months

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[To Be Committed] Various fixes for capability IFUNCs

by Matthew Malcomson

1) Enable having a CAPINIT relocation against an IFUNC. We update the `final_link_relocate` switch case around IFUNC's to also handle CAPINIT relocations. The handling of CAPINIT relocations is slightly different than for AARCH64_NN (i.e. ABS64) relocations since we generally need to emit a dynamic relocation. Handling this relocation also needs to manage the PDE case when a hard-coded address has been put into code to satisfy something like an `adrp`. In these cases the canonical address of the IFUNC becomes its PLT stub rather than the result of the resolver. We then need to use a RELATIVE relocation rather than an IRELATIVE one. N.b. unlike the ABS64 relocation, since a CAPINIT will always emit a dynamic relocation we do not require pointer equality adjustments on a symbol from having seen a CAPINIT. That means we do not need to request that the PLT stub of an IFUNC is treated as the canonical address just from having seen a CAPINIT relocation. A CAPINIT relocation against an IFUNC needs to be recorded internally so that _bfd_elf_allocate_ifunc_dyn_relocs does not garbage collect the PLT stub and associated IRELATIVE relocation. See changes in the CAPINIT case of the IFUNC switch of elfNN_aarch64_final_link_relocate, and in the CAPINIT case of elfNN_aarch64_check_relocs. 2) Ensure that GOT relocations against an IFUNC have their fragment populated with the LSB set. For GOT relocations against a capability IFUNC we need to introduce a relocation for the runtime to provide us with a valid capability. See changes in the GOT cases of the IFUNC switch of elfNN_aarch64_final_link_relocate, changes in the elfNN_aarch64_allocate_ifunc_dynrelocs function, and changes around handling an IFUNC GOT entry in elfNN_aarch64_finish_dynamic_symbol. 3) Ensure that mapping symbols are emitted for the .iplt. Without this many of the testcases here are disassembled incorrectly. See changes in elfNN_aarch64_output_arch_local_syms. 4) IRELATIVE relocations are against symbols which are not in the dynamic symbol table, hence they need their fragment populated to inform the dynamic linker the bounds and permissions to call the associated resolver with. See part of the CAPINIT IFUNC handling in elfNN_aarch64_final_link_relocate, and the IRELATIVE handling in elfNN_aarch64_create_small_pltn_entry. 5) Disallow an ABS64 relocation against a purecap IFUNC. Such a relocation is expecting a 64-bit value but the function will return a capability. Some handling could be implemented by some communication method to the dynamic linker that this particular value should be 64-bit (maybe by emitting an AARCH64_IRELATIVE relocation rather than a MORELLO_IRELATIVE one), but as yet GCC doesn't generate such a relocation and we believe it's unlikely to be needed. See new error check in AARCH64_NN clause of elfNN_aarch64_final_link_relocate. 6) Ensure that for statically linked PDE's, we segregate IRELATIVE and RELATIVE relocations. IRELATIVE relocs should be in the .rela.iplt section, while RELATIVE relocs should be in the .rela.dyn section. Correspondingly all RELATIVE relocations should be between the __rela_dyn_{start,end} symbols, and all IRELATIVE relocations should be between the __rela_iplt_{start,end} symbols. This segregation is made based on dynamic relocation type rather than static relocation that generates it. The segregation allows the static libc to more easily handle relocations. Update testcases accordingly. We introduce some new testcases, morello-ifunc.s contains uses of an IFUNC which has been referenced directly in code. When compiling a PDE this triggers the pointer equality requirement and hence the canonical address for this symbol becomes the PLT stub rather than the result of the resolver. morello-ifunc1.s does not use the IFUNC directly in code so that the address used everywhere is the result of the resolver. Both of these have testcases assembled and linked for static, dynamically linked PDE, and PIE. The testcase without a hard-coded access also has a testcase for -shared. morello-ifunc2.s is written to check that a CAPINIT relocation does indeed stop the garbage collection of an IFUNC's PLT and IRELATIVE relocation. morello-ifunc3.s tests that we error on an ABS64 relocation against a C64 IFUNC. morello-ifunc-dynlink.s tests that a CAPINIT relocation against an IFUNC symbol defined in a shared library behaves the same way as one against a FUNC symbol defined in a shared library. Implementation note: When segregating IRELATIVE and RELATIVE relocs the change for relocations against IFUNC symbols populated in the GOT is straightforward. For CAPINIT relocations the change is not as straightforward. The problem is that on sight of CAPINIT relocations in check_relocs we immediately allocate space in the srelcaps section. In trying to satisfy the above we need to know whether we're going to be emitting an IRELATIVE relocation or RELATIVE one in order to know which section it should go in. The determining factor between these two kinds of relocations is whether there is a text relocation to this IFUNC symbol, since that determines whether we need to make this CAPINIT relocation a RELATIVE relocation pointing to the PLT stub (in order to satisfy pointer equality) or an IRELATIVE relocation pointing to the resolver. Whether such a relocation occurs is recorded against each symbol in the pointer_equality_needed member. This can only be known after all relocations have been seen in check_relocs. Hence, when coming across a CAPINIT relocation in check_relocs we do not in general know whether this CAPINIT relocation should end up as an IRELATIVE or RELATIVE relocation. This patch postpones the decision by recording the number of CAPINIT relocations against a given symbol in a hash table while going through check_relocs and allocating the relevant space in the required section in size_dynamic_sections. N.b. this is similar in purpose to the dyn_relocs linked list on a symbol. We do not use that existing member which is on every symbol since the structure does not allow any indication of what kind of relocation triggered the need. Moreover the structure is used for different purposes throughout the linker and disentangling the new meaning from the existing ones seems overly confusing. Overall, the decisions about which sections relocations against an IFUNC should go in are: CAPINIT relocations: If this is a static PDE link, and the symbol does not need pointer equality handling, then this should emit an IRELATIVE relocation and that should go in the .rela.iplt section. If this is a PIC link, then this should go in the .rela.ifunc section (along with all other dynamic relocations against the IFUNC, as commented in _bfd_elf_allocate_ifunc_dyn_relocs). Otherwise this relocation should go in the srelcaps section (which goes in .rela.dyn). GOT relocations: If this is a static PDE link, and the symbol does not need pointer equality, then this should emit an IRELATIVE relocation into the .rela.iplt section. If this is a static PDE link, then this should emit a RELATIVE relocation and that should go in the srelcaps section (which is in .rela.dyn). Otherwise this should go in .rela.got section.

1 year, 6 months

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[PATCH] ld, aarch64: Account for stubs in bounds sizing

by Alex Coplan

Hi, This patch deals with the interaction between the code that attempts to make bounds precise (for both the PCC bounds and for some individual sections) and the code that adds stubs (e.g. long-branch veneers and interworking stubs) in the AArch64 backend. We aim to set precise bounds for the PCC span and some individual sections in elfNN_c64_resize_sections. However, it transpires that elfNN_aarch64_size_stubs can change the layout in ways that extend sections that should be covered under the PCC span outside of the bounds set in elfNN_c64_resize_sections. The introduction of stubs can also change (even reduce) the amount of padding required to make the bounds on any given section precise. To address this problem, we move the core logic from elfNN_c64_size_sections into a new function, c64_resize_sections, that is safe to be called repeatedly. Similarly, we move the core logic from elfNN_aarch64_size_stubs into a new function aarch64_size_stubs which again can be called repeatedly. We then adjust elfNN_aarch64_size_stubs to call aarch64_size_stubs and c64_resize_sections in a loop, stopping when c64_resize_sections no longer makes any changes to the layout. An important observation made above is that the introduction of stubs can change the amount of padding needed to make bounds precise. Likewise, introducing padding can in theory necessitate the introduction of stubs (e.g. if the change in layout necessitates a long-branch veneer). This is why we run the resizing/stubs code in a loop until no further changes are necessary. Since the amount of padding needed to achieve precise bounds for a section can change (indeed reduce) with the introduction of stubs, we need a mechanism to update the amount of padding applied to a section in a subsequent iteration of c64_resize_sections. We achieve this by introducing a new interface in ld/emultempl/aarch64elf.em. We have the functions: static void c64_set_section_padding (asection *osec, bfd_vma padding, void **cookie); static void c64_get_section_padding (void *cookie); Here, the "cookie" value is, to consumers of this interface (i.e. bfd/elfnn-aarch64.c), an opaque handle used to refer to the padding that was introduced for a given section. The consuming code then passes back the cookie to later query the amount of padding already installed or to update the amount of padding. Internally, within aarch64elf.em, the "cookie" is just a pointer to the node in the ldexp tree containing the integer amount of padding inserted. In the AArch64 ELF backend, we then maintain a (lazily-allocated) mapping between output sections and cookies in order to be able to update the padding we installed in subsequent iterations of c64_resize_sections. While working on this patch, an edge case became apparent: the case where pcc_high_sec requires precise bounds (i.e. where we call ensure_precisely_bounded_section on pcc_high_sec). As it stands, in this case, the code to ensure precise PCC bounds may in fact make the bounds on pcc_high_sec itself no longer representable (even if we previously ensured this by calling ensure_precisely_bounded_section). In general, it is not always possible to choose an amount of padding to add to the end of pcc_high_sec to make both pcc_high_sec and the PCC span itself have precise bounds (without introducing an unreasonably large alignment requirement on pcc_high_sec). To handle the edge case above, we decouple these two problems by adding a separate amount of padding *after* pcc_high_sec to make the PCC bounds precise. If pcc_high_sec is required to have precise bounds, then that can be done in the usual way by adding padding to pcc_high_sec in ensure_precisely_bounded_section. The new mechanism for adding padding after an output section is implemented in aarch64elf.em:c64_pad_after_section. To avoid having to add yet another mechanism to update the padding *after* pcc_high_sec, we avoid adding this padding until all other resizing / bounds-setting work is done. This is not possible for individual sections since padding introduced there may have a knock-on effect requiring further work, but we believe this isn't the case for the padding added after pcc_high_sec to make the PCC bounds precise. This patch also reveals a pre-existing issue whereby we end up calling ensure_precisely_bounded_section on the *ABS* section. Without a further change to prevent this, this can lead to a null pointer dereference in ensure_precisely_bounded_section, since the "owner" field on the *ABS* pointer is NULL, and we use this field to obtain a pointer to the output BFD in the new c64_get_section_padding_info function. Of course, it doesn't make sense for ensure_precisely_bounded_section to be called on the *ABS* section in the first place. This can happen when there are relocations against ldscript-defined symbols which are defined at the top level of the ldscript (i.e. not in a particular output section). Those symbols initially have their output section set to the *ABS* section. Later, we resolve such symbols to their correct output section in ldexp_finalize_syms, but the code in c64_resize_sections is running in ldemul_after_allocation, which comes before the call to ldexp_finalize_syms in the lang_process flow. For now, we just skip such symbols when looking for sections that need precise bounds in c64_resize_sections, but this issue will later need fixing properly. We choose to avoid fixing the pre-existing issue in this patch to avoid over-complicating an already complex change. Tested on aarch64-none-elf and aarch64-none-linux-gnu, OK for the Morello branch? Thanks, Alex

1 year, 7 months

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[To be committed]: Make various linker tests more robust

by Matthew Malcomson

Various linker tests have been failing on aarch64-none-linux-gnu for a while now. We've ignored their failure since we knew they were from us writing the tests with hard-coded values based on the aarch64-none-elf toolchain. A while ago we introduced a record/check feature in the testsuite that has allowed re-writing some tests in a more general manner. This commit adjusts the remaining tests using this new feature. While updating these remaining tests we also changed the record/check feature to replace *all* occurrences of a `check` pattern in the line we want to use. This seems like what would be the expected behaviour, although we did not actually need that change in this commit. Only one testcase was slightly tricky to generalise. This was the `morello-pcc-bounds-include-readonly` testcase. We wanted to ensure that the `othersection` was included in PCC bounds, but that othersection was usually not the last RO section. Since it was usually not the last RO section we could not calculate the bounds that should be given to our capability. When using hard-coded addresses this was fine since we could just ensure that the hard-coded address was large enough to span .othersection. The record/check functionality does not allow checking that a value is acceptable (i.e. the "check" part does not pass the values we see to some procedure). Rather it generates a value that the line should match. Hence in order to make this particular test general we emitted the section headers, found the last read-only section, then asserted that the size of the capability with executable permissions spanned up to the end of that section. The method by which we find the last read-only section could change between different targets, but it at least works on both aarch64-none-elf and aarch64-none-linux. ############### Attachment also inlined for ease of reply ############### diff --git a/binutils/testsuite/lib/binutils-common.exp b/binutils/testsuite/lib/binutils-common.exp index 422cb327e0e59e61a86fc4712e6ba3db4cb3edcd..a4deb7ad39b933bff33520c42c0002189ca439f0 100644 --- a/binutils/testsuite/lib/binutils-common.exp +++ b/binutils/testsuite/lib/binutils-common.exp @@ -465,7 +465,7 @@ proc regexp_diff { file_1 file_2 args } { } foreach {name value} $extra_subst { set value [eval $value]; - regsub -- $name $line_bx $value line_bx + regsub -all -- $name $line_bx $value line_bx } verbose "looking for $n\"^$line_bx$\"" 3 while { [expr [regexp "^$line_bx$" "$line_a" PREVMATCH {*}$extra_vars] == $negated] } { @@ -489,7 +489,7 @@ proc regexp_diff { file_1 file_2 args } { } foreach {name value} $extra_subst { set value [eval $value]; - regsub -- $name $line_bx $value line_bx + regsub -all -- $name $line_bx $value line_bx } verbose "optional match for $n\"^$line_bx$\"" 3 if { [expr [regexp "^$line_bx$" "$line_a" PREVMATCH {*}$extra_vars] != $negated] } { @@ -555,7 +555,7 @@ proc regexp_diff { file_1 file_2 args } { set value [eval $value]; # send_user "match: $name\n" # send_user "replacement: $value\n" - regsub -- $name $line_bx $value line_bx + regsub -all -- $name $line_bx $value line_bx } # send_user "checking against $line_bx\n" verbose "regexp $n\"^$line_bx$\"\nline \"$line_a\"" 3 diff --git a/ld/testsuite/ld-aarch64/aarch64-elf.exp b/ld/testsuite/ld-aarch64/aarch64-elf.exp index a4d5495b22ea9913d4ce6da98aadcb3289b77da2..c48164d9cb358e4eb5f21fbdebe20f3610cdf3be 100644 --- a/ld/testsuite/ld-aarch64/aarch64-elf.exp +++ b/ld/testsuite/ld-aarch64/aarch64-elf.exp @@ -99,13 +99,16 @@ proc aarch64_required_func_addend { base result } { proc aarch64_page_plus_offset { page offset } { return [format %x [expr "0x$page + 0x$offset"] ]; } +proc aarch64_page_plus_decimal_offset { page offset } { + return [format %x [expr "0x$page + $offset"] ]; +} # Return the 8-hexdigit truncation of an address. proc aarch64_8digit_addr { addr { plusLSB 0 } } { if { $plusLSB } { return [aarch64_8digit_addr [format %08x [expr "0x$addr + 1"]]]; } - return [string range "$addr" end-7 end]; + return [format %08x "0x$addr"]; } set eh-frame-merge-lp64 [list [list "EH Frame merge" \ diff --git a/ld/testsuite/ld-aarch64/c64-ifunc-3a.d b/ld/testsuite/ld-aarch64/c64-ifunc-3a.d index bd36b23545e800cd5d952d730ac36ad3c40d0a31..7690b42edd576039c6e455fcf5bb7a480ee0f8bd 100644 --- a/ld/testsuite/ld-aarch64/c64-ifunc-3a.d +++ b/ld/testsuite/ld-aarch64/c64-ifunc-3a.d @@ -5,7 +5,11 @@ #objdump: -dw #... -0+(150|1d0|1e8|200) <__GI_foo>: +Disassembly of section \.text: + +#record: INDIRECT_FOO +([0-9a-f]+) <__GI_foo>: +#check: FOO_POS format %x 0x$INDIRECT_FOO #... -[ \t0-9a-f]+:[ \t0-9a-f]+bl[ \t0-9a-f]+<\*ABS\*\+0x(150|1d0|1e8|200)@plt> +[ \t0-9a-f]+:[ \t0-9a-f]+bl[ \t0-9a-f]+<\*ABS\*\+0xFOO_POS@plt> #pass diff --git a/ld/testsuite/ld-aarch64/emit-morello-reloc-markers-1.d b/ld/testsuite/ld-aarch64/emit-morello-reloc-markers-1.d index b8474f996fee97befacaf2f3366e2f1ef6a6885d..a5f0d9696cd849a3b092263e8fa09daaa6628869 100644 --- a/ld/testsuite/ld-aarch64/emit-morello-reloc-markers-1.d +++ b/ld/testsuite/ld-aarch64/emit-morello-reloc-markers-1.d @@ -11,9 +11,13 @@ Sections: Idx Name Size VMA LMA File off Algn - 0 \.rela\.dyn 00000018 0000000000000000 0000000000000000 00010000 2\*\*3 +#record: RELADYN_START + 0 \.rela\.dyn 00000018 ([0-9a-f]+) .* .* 2\*\*3 CONTENTS, ALLOC, LOAD, READONLY, DATA + +#check: STARTPOS string tolower $RELADYN_START +#check: ENDPOS format %016x [expr "0x$RELADYN_START + 0x18"] SYMBOL TABLE: -0000000000000000 l d \.rela\.dyn 0000000000000000 \.rela\.dyn -0000000000000018 l O \.rela\.dyn 0000000000000000 __rela_dyn_end -0000000000000000 l O \.rela\.dyn 0000000000000000 __rela_dyn_start +STARTPOS l d \.rela\.dyn 0000000000000000 \.rela\.dyn +ENDPOS l O \.rela\.dyn 0000000000000000 __rela_dyn_end +STARTPOS l O \.rela\.dyn 0000000000000000 __rela_dyn_start diff --git a/ld/testsuite/ld-aarch64/emit-morello-reloc-markers-2.d b/ld/testsuite/ld-aarch64/emit-morello-reloc-markers-2.d index f65f859deaa51c442079a4b0b4598b499b32e4bc..e855bc55a4fd91579250ba069c91314446162eb9 100644 --- a/ld/testsuite/ld-aarch64/emit-morello-reloc-markers-2.d +++ b/ld/testsuite/ld-aarch64/emit-morello-reloc-markers-2.d @@ -12,14 +12,17 @@ Sections: Idx Name Size VMA LMA File off Algn - 0 \.rela\.dyn 00000030 0000000000000000 0000000000000000 00010000 .* +#record: RELADYN_START + 0 \.rela\.dyn 00000030 ([0-9a-f]+) .* .* .* CONTENTS, ALLOC, LOAD, READONLY, DATA .* \.got .* .* +#check: STARTPOS string tolower $RELADYN_START +#check: ENDPOS format %016x [expr "0x$RELADYN_START + 0x30"] SYMBOL TABLE: -0000000000000000 l d \.rela\.dyn 0000000000000000 \.rela\.dyn +STARTPOS l d \.rela\.dyn 0000000000000000 \.rela\.dyn .* -0000000000000030 l O \.rela\.dyn 0000000000000000 __rela_dyn_end -0000000000000000 l O \.rela\.dyn 0000000000000000 __rela_dyn_start +ENDPOS l O \.rela\.dyn 0000000000000000 __rela_dyn_end +STARTPOS l O \.rela\.dyn 0000000000000000 __rela_dyn_start #pass diff --git a/ld/testsuite/ld-aarch64/emit-morello-reloc-markers-3.d b/ld/testsuite/ld-aarch64/emit-morello-reloc-markers-3.d index ea373cd24260c330ef92e836705fafc0392fd74b..e60908921b0246f184e5a481f9e288b0ac8bb9e9 100644 --- a/ld/testsuite/ld-aarch64/emit-morello-reloc-markers-3.d +++ b/ld/testsuite/ld-aarch64/emit-morello-reloc-markers-3.d @@ -12,14 +12,17 @@ Sections: Idx Name Size VMA LMA File off Algn - 0 \.rela\.dyn 00000018 0000000000000000 0000000000000000 00010000 .* +#record: RELADYN_START + 0 \.rela\.dyn 00000018 ([0-9a-f]+) .* .* .* CONTENTS, ALLOC, LOAD, READONLY, DATA .* \.got .* .* +#check: STARTPOS string tolower $RELADYN_START +#check: ENDPOS format %016x [expr "0x$RELADYN_START + 0x18"] SYMBOL TABLE: -0000000000000000 l d \.rela\.dyn 0000000000000000 \.rela\.dyn +STARTPOS l d \.rela\.dyn 0000000000000000 \.rela\.dyn .* -0000000000000018 l O \.rela\.dyn 0000000000000000 __rela_dyn_end -0000000000000000 l O \.rela\.dyn 0000000000000000 __rela_dyn_start +ENDPOS l O \.rela\.dyn 0000000000000000 __rela_dyn_end +STARTPOS l O \.rela\.dyn 0000000000000000 __rela_dyn_start #pass diff --git a/ld/testsuite/ld-aarch64/emit-relocs-morello-7.d b/ld/testsuite/ld-aarch64/emit-relocs-morello-7.d index c32d307eb7e05d5c5d06944f09b823246f8e9474..0421fea138762b2431611966f1084b44c0bc8ab4 100644 --- a/ld/testsuite/ld-aarch64/emit-relocs-morello-7.d +++ b/ld/testsuite/ld-aarch64/emit-relocs-morello-7.d @@ -10,58 +10,80 @@ # we want to ensure a direct link between the relevant relocations and their # GOT entries. # -# Point here is that the __text_start and __data_other symbols should end up -# pointing into the text section, which should mean that they have PCC bounds -# and the value of the __data_other symbol should include an addend. These are -# the symbols used in the first and last LDR's in the function. +# As far as the linker is concerned, each of the symbols defined in our linker +# script are associated with the output section just before them. However, we +# add a hack for symbols which are named in the pattern __*_start so that their +# Morello bounds are given as if the symbol was associated with the section just +# after them. +# +# Hence the __text_start and __data_other symbols should end up with permissions +# for the text section. This should mean that they have PCC bounds, and the +# value of the __data_other symbol should include an addend. These are the +# symbols used in the first and last LDR instructions in the function. # # Meanwhile, the __text_other symbol should have bounds of everything remaining # in the section *before* it (which is nothing), and the __data_start symbol -# should have bounds spanning the entire section *after* it (which happens to -# be the .interp section). +# should have bounds spanning the entire section *after* it (the .data section). # #source: emit-relocs-morello-7.s #as: -march=morello+c64 #ld: -static -pie -T emit-relocs-morello-7.ld -#objdump: -DR -j .text -j .data -j .got +#objdump: -DR --section-headers -j .text -j .got -j .data .*: file format .* +Sections: +Idx Name Size VMA LMA File off Algn +#record: TEXT_START +.* .text 00000010 ([0-9a-f]+) .* .* 2\*\*2 + CONTENTS, ALLOC, LOAD, READONLY, CODE +#record: DATA_START +.* .data 00000004 ([0-9a-f]+) .* .* 2\*\*0 + CONTENTS, ALLOC, LOAD, DATA +.* .got 00000050 0000000000001000 0000000000001000 00001000 2\*\*4 + CONTENTS, ALLOC, LOAD, DATA + +#check: TXT_START string tolower $TEXT_START +#check: DTA_START string tolower $DATA_START Disassembly of section \.text: -0000000000000230 <obj>: +TXT_START <obj>: .*: c2400400 ldr c0, \[c0, #16\] .*: c2401000 ldr c0, \[c0, #64\] .*: c2400c00 ldr c0, \[c0, #48\] .*: c2400800 ldr c0, \[c0, #32\] + Disassembly of section \.data: -.* <\.data>: +DTA_START <\.data>: .*: 0000000a .* Disassembly of section \.got: +#check: PCC_START aarch64_8digit_addr $TEXT_START +#check: DAT_START aarch64_8digit_addr $DATA_START +#check: PCC_LENGTH aarch64_8digit_addr [format %x [expr "0x1050 - 0x$TEXT_START"]] 0000000000001000 <\.got>: 1000: [0-9a-f]+ .* \.\.\. - 1010: 00000230 .* + 1010: PCC_START .* 1010: R_MORELLO_RELATIVE \*ABS\* 1014: 00000000 .* - 1018: 00000e20 .* + 1018: PCC_LENGTH .* 101c: 04000000 .* - 1020: 00000230 .* + 1020: PCC_START .* 1020: R_MORELLO_RELATIVE \*ABS\*\+0x10 1024: 00000000 .* - 1028: 00000e20 .* + 1028: PCC_LENGTH .* 102c: 04000000 .* - 1030: 00000240 .* + 1030: DAT_START .* 1030: R_MORELLO_RELATIVE \*ABS\* 1034: 00000000 .* - 1038: 0000000d .* - 103c: 01000000 .* - 1040: 00000230 .* + 1038: 00000004 .* + 103c: 02000000 .* + 1040: PCC_START .* 1040: R_MORELLO_RELATIVE \*ABS\* \.\.\. 104c: 02000000 .* diff --git a/ld/testsuite/ld-aarch64/emit-relocs-morello-7.ld b/ld/testsuite/ld-aarch64/emit-relocs-morello-7.ld index 1402e98ef080a4b9d77fb91dbb22208e0cd0e28e..53294c012593e6ad4850a97492a3c00804e9c6e0 100644 --- a/ld/testsuite/ld-aarch64/emit-relocs-morello-7.ld +++ b/ld/testsuite/ld-aarch64/emit-relocs-morello-7.ld @@ -5,8 +5,11 @@ SECTIONS { __text_start = .; __text_other = .; .text : { *(.text) } - __data_start = .; __data_other = .; + /* Try and collect all read-only stuff so that the data symbols stay at + * the start of the .data section. */ + .rodata : ONLY_IF_RO { *(.*) } + __data_start = .; .data : { *(.data) } . = ALIGN(0x1000); .got : { *(.got) } diff --git a/ld/testsuite/ld-aarch64/emit-relocs-morello-9.d b/ld/testsuite/ld-aarch64/emit-relocs-morello-9.d index a9e1c3f37485df9d0ea9f2a52edab97cc9edf355..18ca9c98816a63713287809556c62d43be89f4bd 100644 --- a/ld/testsuite/ld-aarch64/emit-relocs-morello-9.d +++ b/ld/testsuite/ld-aarch64/emit-relocs-morello-9.d @@ -1,3 +1,6 @@ +# Checking that the LSB is set on all relocations to a function symbol where +# the relocations are there to load an address into a register (rather than +# jump to a relative address). #source: emit-relocs-morello-9.s #as: -march=morello+c64 #ld: -static -Ttext-segment 0x0 @@ -8,26 +11,29 @@ Disassembly of section \.text: -0000000000000000 <_start>: - 0: f2800020 movk x0, #0x1 - 4: f2800020 movk x0, #0x1 - 8: 30ffffc0 adr c0, 1 <_start\+0x1> - c: 30ffffa0 adr c0, 1 <_start\+0x1> - 10: 02000400 add c0, c0, #0x1 - 14: 02000400 add c0, c0, #0x1 - 18: d2800020 mov x0, #0x1 // #1 - 1c: d2800020 mov x0, #0x1 // #1 - 20: f2800020 movk x0, #0x1 - 24: f2800020 movk x0, #0x1 +#record: TEXT_START +([0-9a-f]+) <_start>: +#check: LOBITS format %x [expr "0x$TEXT_START + 1"] +.*: ........ movk x0, #0xLOBITS +.*: ........ movk x0, #0xLOBITS +.*: ........ adr c0, LOBITS <_start\+0x1> +.*: ........ adr c0, LOBITS <_start\+0x1> +.*: ........ add c0, c0, #0xLOBITS +.*: ........ add c0, c0, #0xLOBITS +.*: ........ mov x0, #0xLOBITS .* +.*: ........ mov x0, #0xLOBITS .* +.*: ........ movk x0, #0xLOBITS +.*: ........ movk x0, #0xLOBITS Disassembly of section \.data: +#check: LO8BITS aarch64_8digit_addr $TEXT_START 1 .* <val>: - .*: 00000001 .word 0x00000001 - .*: 00000001 .word 0x00000001 - .*: 00000001 .word 0x00000001 + .*: LO8BITS .word 0xLO8BITS + .*: LO8BITS .word 0xLO8BITS + .*: LO8BITS .word 0xLO8BITS .*: 00000000 .word 0x00000000 - .*: 00000001 .word 0x00000001 - .*: 00000001 .word 0x00000001 - .*: 00000001 .word 0x00000001 + .*: LO8BITS .word 0xLO8BITS + .*: LO8BITS .word 0xLO8BITS + .*: LO8BITS .word 0xLO8BITS .*: 00000000 .word 0x00000000 diff --git a/ld/testsuite/ld-aarch64/morello-pcc-bounds-include-readonly.d b/ld/testsuite/ld-aarch64/morello-pcc-bounds-include-readonly.d index 9c4aa81b9699a03dc4f661d86323a15532180d4f..1aa3f8e202d9f6fb74f721952980a2f6990be610 100644 --- a/ld/testsuite/ld-aarch64/morello-pcc-bounds-include-readonly.d +++ b/ld/testsuite/ld-aarch64/morello-pcc-bounds-include-readonly.d @@ -13,27 +13,31 @@ #source: morello-pcc-bounds-include-readonly.s #as: -march=morello+c64 #ld: -static -pie -T morello-pcc-bounds-include-readonly.ld -#objdump: -j .data -j .text -j .othersection -DR +#objdump: -DR --section-headers .*: file format .* +Sections: +Idx Name Size VMA LMA File off Algn +.* \.text 00000010 00000000000001a0 00000000000001a0 000001a0 2\*\*5 +#record: LAST_RO_SIZE LAST_RO_VMA +#... + +[0-9]+ \.rela\.dyn +([0-9a-f]+) ([0-9a-f]+) .* + + CONTENTS, ALLOC, LOAD, READONLY, DATA + +[0-9]+ \.data .* +#... Disassembly of section \.text: 00000000000001a0 <obj>: #... +Disassembly of section \.data: -Disassembly of section .othersection: - -0000000000012000 <othersection_start>: -#... - -Disassembly of section .data: - +#check: PCC_SIZE format %08x [expr "0x$LAST_RO_VMA + 0x$LAST_RO_SIZE - 0x1a0"] 0000000000014000 <data_start>: - [0-9a-f]+: 000001a0 udf #416 + [0-9a-f]+: 000001a0 .* 14000: R_MORELLO_RELATIVE \*ABS\* - [0-9a-f]+: 00000000 udf #0 - [0-9a-f]+: 00011f00 \.inst 0x00011f00 ; undefined + [0-9a-f]+: 00000000 .* + [0-9a-f]+: PCC_SIZE .* [0-9a-f]+: 04000000 add z0\.b, p0/m, z0\.b, z0\.b diff --git a/ld/testsuite/ld-aarch64/morello-sizeless-global-syms.d b/ld/testsuite/ld-aarch64/morello-sizeless-global-syms.d index 89c7963b789dba65b7bb00c07c7197bb5759a8d9..51877627255c2f41dd27e077c54424bc7ae47f38 100644 --- a/ld/testsuite/ld-aarch64/morello-sizeless-global-syms.d +++ b/ld/testsuite/ld-aarch64/morello-sizeless-global-syms.d @@ -9,34 +9,40 @@ Disassembly of section \.data: [0-9a-f]+ <ptr3>: - [0-9a-f]+: 00010450.* +#record: BSS_START + [0-9a-f]+: ([0-9a-f]+) .* [0-9a-f]+: R_MORELLO_RELATIVE \*ABS\* [0-9a-f]+: 00000000.* [0-9a-f]+: 00000000.* [0-9a-f]+: 02000000.* [0-9a-f]+ <ptr2>: - [0-9a-f]+: 00010454.* +#check: BAR_POS format %08x [expr "0x$BSS_START + 0x4"] + [0-9a-f]+: BAR_POS .* [0-9a-f]+: R_MORELLO_RELATIVE \*ABS\* [0-9a-f]+: 00000000.* [0-9a-f]+: 00000000.* [0-9a-f]+: 02000000.* [0-9a-f]+ <ptr1>: - [0-9a-f]+: 00010458.* +#check: FOO_POS format %08x [expr "0x$BSS_START + 0x8"] + [0-9a-f]+: FOO_POS .* [0-9a-f]+: R_MORELLO_RELATIVE \*ABS\* [0-9a-f]+: 00000000.* [0-9a-f]+: 00000000.* [0-9a-f]+: 02000000.* -Disassembly of section .bss: +Disassembly of section \.bss: -0000000000010450 <baz>: +#check: BAZL_POS format %016x 0x$BSS_START +#check: BARL_POS format %016x [expr "0x$BSS_START + 0x4"] +#check: FOOL_POS format %016x [expr "0x$BSS_START + 0x8"] +BAZL_POS <baz>: [0-9a-f]+: 00000000.* -[0-9a-f]+ <bar>: +BARL_POS <bar>: [0-9a-f]+: 00000000.* -[0-9a-f]+ <foo>: +FOOL_POS <foo>: [0-9a-f]+: 00000000.* [0-9a-f]+: 00000000.* diff --git a/ld/testsuite/ld-aarch64/morello-sizeless-got-syms.d b/ld/testsuite/ld-aarch64/morello-sizeless-got-syms.d index 82131d11dde1995214bff673c46d925facd2650b..06ed9d2af559ee7f10e22ca23092752dd664ef98 100644 --- a/ld/testsuite/ld-aarch64/morello-sizeless-got-syms.d +++ b/ld/testsuite/ld-aarch64/morello-sizeless-got-syms.d @@ -1,3 +1,8 @@ +# Checking that: +# 1) Text references entries in the GOT which correspond to the relevant +# symbols. +# 2) The size requested for those capabilities in the GOT is zero (matching +# the size of the symbols). #source: morello-sizeless-got-syms.s #as: -march=morello+c64 #ld: -static -pie @@ -8,18 +13,23 @@ Disassembly of section \.text: [0-9a-f]+ <get_foo>: - [0-9a-f]+: 90800080 adrp c0, 10000 .* - [0-9a-f]+: c240dc00 ldr c0, \[c0, #880\] +#record: GOT_PAGE + [0-9a-f]+: ........ adrp c0, ([0-9a-f]+) .* +#record: FOO_OFFSET + [0-9a-f]+: ........ ldr c0, \[c0, #([0-9]+)\] [0-9a-f]+: c2c253c0 ret c30 +#check: GOTPAGE string tolower $GOT_PAGE [0-9a-f]+ <get_bar>: - [0-9a-f]+: 90800080 adrp c0, 10000 .* - [0-9a-f]+: c240e000 ldr c0, \[c0, #896\] + [0-9a-f]+: ........ adrp c0, GOTPAGE .* +#record: BAR_OFFSET + [0-9a-f]+: ........ ldr c0, \[c0, #([0-9]+)\] [0-9a-f]+: c2c253c0 ret c30 [0-9a-f]+ <get_baz>: - [0-9a-f]+: 90800080 adrp c0, 10000 .* - [0-9a-f]+: c240d800 ldr c0, \[c0, #864\] + [0-9a-f]+: ........ adrp c0, GOTPAGE .* +#record: BAZ_OFFSET + [0-9a-f]+: ........ ldr c0, \[c0, #([0-9]+)\] [0-9a-f]+: c2c253c0 ret c30 [0-9a-f]+ <_start>: @@ -27,35 +37,44 @@ Disassembly of section \.text: Disassembly of section \.got: -0000000000010350 <\.got>: - [0-9a-f]+: .* - [0-9a-f]+: .* - [0-9a-f]+: .* - [0-9a-f]+: .* - [0-9a-f]+: 000103c0 .* +#check: FOO_GOTPOS aarch64_page_plus_decimal_offset $GOT_PAGE $FOO_OFFSET +#check: BAR_GOTPOS aarch64_page_plus_decimal_offset $GOT_PAGE $BAR_OFFSET +#check: BAZ_GOTPOS aarch64_page_plus_decimal_offset $GOT_PAGE $BAZ_OFFSET +[0-9a-f]+ <\.got>: + +[0-9a-f]+: .* + +[0-9a-f]+: .* + +[0-9a-f]+: .* + +[0-9a-f]+: .* +#record: BAZPOS + +BAZ_GOTPOS: ([0-9a-f]+) .* [0-9a-f]+: R_MORELLO_RELATIVE \*ABS\* - [0-9a-f]+: 00000000 .* - [0-9a-f]+: 00000000 .* - [0-9a-f]+: 02000000 .* - [0-9a-f]+: 000103c8 .* + +[0-9a-f]+: 00000000 .* + +[0-9a-f]+: 00000000 .* + +[0-9a-f]+: 02000000 .* +#record: FOOPOS + +FOO_GOTPOS: ([0-9a-f]+) .* [0-9a-f]+: R_MORELLO_RELATIVE \*ABS\* - [0-9a-f]+: 00000000 .* - [0-9a-f]+: 00000000 .* - [0-9a-f]+: 02000000 .* - [0-9a-f]+: 000103c4 .* + +[0-9a-f]+: 00000000 .* + +[0-9a-f]+: 00000000 .* + +[0-9a-f]+: 02000000 .* +#record: BARPOS + +BAR_GOTPOS: ([0-9a-f]+) .* [0-9a-f]+: R_MORELLO_RELATIVE \*ABS\* - [0-9a-f]+: 00000000 .* - [0-9a-f]+: 00000000 .* - [0-9a-f]+: 02000000 .* + +[0-9a-f]+: 00000000 .* + +[0-9a-f]+: 00000000 .* + +[0-9a-f]+: 02000000 .* Disassembly of section .bss: -00000000000103c0 <baz>: +#check: FOO_LONG_POS format %016x 0x$FOOPOS +#check: BAR_LONG_POS format %016x 0x$BARPOS +#check: BAZ_LONG_POS format %016x 0x$BAZPOS +BAZ_LONG_POS <baz>: [0-9a-f]+: 00000000 .* -[0-9a-f]+ <bar>: +BAR_LONG_POS <bar>: [0-9a-f]+: 00000000 .* -[0-9a-f]+ <foo>: +FOO_LONG_POS <foo>: [0-9a-f]+: 00000000 .* [0-9a-f]+: 00000000 .* diff --git a/ld/testsuite/ld-aarch64/morello-sizeless-local-syms.d b/ld/testsuite/ld-aarch64/morello-sizeless-local-syms.d index 2f74b7a643ded8078e206daf81b40997705926ba..0f0fbb586d0514ebf55e29a8e6448427c7223248 100644 --- a/ld/testsuite/ld-aarch64/morello-sizeless-local-syms.d +++ b/ld/testsuite/ld-aarch64/morello-sizeless-local-syms.d @@ -9,34 +9,40 @@ Disassembly of section .data: [0-9a-f]+ <ptr3>: - [0-9a-f]+: 00010450.* +#record: BSS_START + [0-9a-f]+: ([0-9a-f]+) .* [0-9a-f]+: R_MORELLO_RELATIVE \*ABS\* [0-9a-f]+: 00000000.* [0-9a-f]+: 00000000.* [0-9a-f]+: 02000000.* [0-9a-f]+ <ptr2>: - [0-9a-f]+: 00010454.* +#check: BAR_POS format %08x [expr "0x$BSS_START + 0x4"] + [0-9a-f]+: BAR_POS .* [0-9a-f]+: R_MORELLO_RELATIVE \*ABS\* [0-9a-f]+: 00000000.* [0-9a-f]+: 00000000.* [0-9a-f]+: 02000000.* [0-9a-f]+ <ptr1>: - [0-9a-f]+: 00010458.* +#check: FOO_POS format %08x [expr "0x$BSS_START + 0x8"] + [0-9a-f]+: FOO_POS .* [0-9a-f]+: R_MORELLO_RELATIVE \*ABS\* [0-9a-f]+: 00000000.* [0-9a-f]+: 00000000.* [0-9a-f]+: 02000000.* -Disassembly of section .bss: +Disassembly of section \.bss: -0000000000010450 <baz>: +#check: BAZL_POS format %016x 0x$BSS_START +#check: BARL_POS format %016x [expr "0x$BSS_START + 0x4"] +#check: FOOL_POS format %016x [expr "0x$BSS_START + 0x8"] +BAZL_POS <baz>: [0-9a-f]+: 00000000.* -[0-9a-f]+ <bar>: +BARL_POS <bar>: [0-9a-f]+: 00000000.* -[0-9a-f]+ <foo>: +FOOL_POS <foo>: [0-9a-f]+: 00000000.* [0-9a-f]+: 00000000.*

1 year, 9 months

1
0
0 0

[To be committed]: Update for new Morello TLS ABI

by Matthew Malcomson

This patch series adds the new features into Morello binutils in order to implement the recently merged TLS ABI update. https://github.com/ARM-software/abi-aa/pull/80 This includes enabling GAS to output the new relocations, enabling the linker to read these relocations, and replacing the existing Morello TLS relaxations with the new versions. A corresponding patch for emitting the new TLS access sequences has been written for GCC and will be pushed at the same time this is committed. Entire patch series attached to cover letter.

1 year, 9 months

1
6
0 0

[To be committed]: Adjust TLS relaxation condition

by Matthew Malcomson

In aarch64_tls_transition_without_check and elfNN_aarch64_tls_relax we choose whether to perform a relaxation to an IE access model or an LE access model based on whether the symbol itself is marked as local (i.e. `h == NULL`). This is problematic in two ways. The first is that sometimes a global dynamic access can be relaxed to an initial exec access when creating a shared library, and if that happens on a local symbol then we currently relax it to a local exec access instead. This usually does not happen since we only relax an access if aarch64_can_relax_tls returns true and aarch64_can_relax_tls does not have the same problem. However, it can happen when we have seen both an IE and GD access on the same symbol. This case is exercised in the newly added testcase tls-relax-gd-ie-2. The second problem is that deciding based on whether the symbol is local misses the case when the symbol is global but is still non-interposable and known to be located in the executable. This happens on all global symbols in executables. This case is exercised in the newly added testcase tls-relax-ie-le-4. Here we adjust the condition we base our relaxation on so that we relax to local-exec if we are creating an executable and the relevant symbol we're accessing is stored inside that executable. Alongside that general fix, we adjust the existing exclusion parameters for Morello relaxations. Patches are in-flight to replace the existing Morello TLS relocation handling with the more recent TLS ABI. This patch simply adjusts the existing handling to use a more robust method to determine the case when a GD -> LE relaxation can be performed. -- Updating tests for new relaxation criteria Many of the tests added to check our relaxation to IE were implemented by taking advantage of the fact that we did not relax a global symbol defined in an executable. Since a global symbol defined in an executable is still not interposable, we know that a TLS version of such a symbol will be in the main TLS block. This means that we can perform a stronger relaxation on such symbols and relax their accesses to a local-exec access. Hence we have to update all tests that relied on the older suboptimal decision making. The two cases when we still would want to relax a general dynamic access to an initial exec one are: 1) When in a shared library and accessing a symbol which we have already seen accessed with an initial exec access sequence. 2) When in an executable and accessing a symbol defined in a shared library. Both of these require shared library support, which means that these tests are now only available on targets with that. I have chosen to switch the existing testcases from a plain executable to one dynamically linked to a shared object as that doesn't require changing the testcases quite so much (just requires accessing a different variable rather than requiring adding another code sequence). The tls-relax-all testcase was an outlier to the above approach, since it included a general dynamic access to both a local and global symbol and inspected for the difference accordingly. This is the same logical change as https://sourceware.org/pipermail/binutils/2022-July/121660.html ############### Attachment also inlined for ease of reply ############### diff --git a/bfd/elfnn-aarch64.c b/bfd/elfnn-aarch64.c index a0898f9e7b9e44ae609bbc0a6eae5eaa830771e2..2d3083f540469365a5a8df1448bf5da2df1762e8 100644 --- a/bfd/elfnn-aarch64.c +++ b/bfd/elfnn-aarch64.c @@ -5814,76 +5814,77 @@ aarch64_tls_transition_without_check (bfd_reloc_code_real_type r_type, struct elf_link_hash_entry *h, bfd_boolean morello_reloc) { - bfd_boolean is_local = h == NULL; + bfd_boolean local_exec = (bfd_link_executable (info) + && SYMBOL_REFERENCES_LOCAL (info, h)); switch (r_type) { case BFD_RELOC_MORELLO_TLSDESC_ADR_PAGE20: - return (is_local || !bfd_link_pic (info) + return (local_exec ? BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1 : r_type); case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21: case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21: - return (is_local + return (local_exec ? BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1 : BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21); case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21: - return (is_local + return (local_exec ? BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC : r_type); case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19: - return (is_local + return (local_exec ? BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1 : BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19); case BFD_RELOC_AARCH64_TLSDESC_LDR: - return (is_local + return (local_exec ? BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC : BFD_RELOC_AARCH64_NONE); case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC: - return (is_local + return (local_exec ? BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC : BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC); case BFD_RELOC_AARCH64_TLSDESC_OFF_G1: - return (is_local + return (local_exec ? BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2 : BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1); case BFD_RELOC_MORELLO_TLSDESC_LD128_LO12: - return ((is_local || !bfd_link_pie (info) - ? BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC : r_type)); + return (local_exec + ? BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC : r_type); case BFD_RELOC_AARCH64_TLSDESC_LDNN_LO12_NC: case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC: - return (is_local + return (local_exec ? BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC : BFD_RELOC_AARCH64_TLSIE_LDNN_GOTTPREL_LO12_NC); case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: - return is_local ? BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1 : r_type; + return local_exec ? BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1 : r_type; case BFD_RELOC_AARCH64_TLSIE_LDNN_GOTTPREL_LO12_NC: - return is_local ? BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC : r_type; + return local_exec ? BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC : r_type; case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19: return r_type; case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21: - return (is_local + return (local_exec ? BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12 : BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19); case BFD_RELOC_MORELLO_TLSDESC_CALL: - return ((is_local || !bfd_link_pie (info)) + return (local_exec ? BFD_RELOC_AARCH64_NONE : r_type); case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12: - if (morello_reloc && !is_local && bfd_link_pie (info)) + if (morello_reloc && !local_exec) return r_type; /* Fall through. */ case BFD_RELOC_AARCH64_TLSDESC_ADD: @@ -5896,16 +5897,16 @@ aarch64_tls_transition_without_check (bfd_reloc_code_real_type r_type, case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC: case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21: case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21: - return is_local ? BFD_RELOC_AARCH64_NONE : r_type; + return local_exec ? BFD_RELOC_AARCH64_NONE : r_type; #if ARCH_SIZE == 64 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC: - return is_local + return local_exec ? BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC : BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC; case BFD_RELOC_AARCH64_TLSGD_MOVW_G1: - return is_local + return local_exec ? BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2 : BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1; #endif @@ -6032,12 +6033,6 @@ aarch64_tls_transition (bfd *input_bfd, && (ELFNN_R_TYPE (rel[1].r_info) == MORELLO_R (TLSDESC_CALL))); - /* GD -> IE is not supported for Morello TLSDESC yet. We do however allow - lowering of GD -> LE for static non-pie executables. XXX It ought to be - safe to do this for A64 as well but it is not implemented yet. */ - if (h != NULL && morello_reloc && bfd_link_pie (info)) - return bfd_r_type; - return aarch64_tls_transition_without_check (bfd_r_type, info, h, morello_reloc); } @@ -7833,8 +7828,8 @@ elfNN_aarch64_tls_relax (bfd *input_bfd, struct bfd_link_info *info, bfd_byte *contents, Elf_Internal_Rela *rel, struct elf_link_hash_entry *h, unsigned long r_symndx) { - bfd_boolean is_local = h == NULL; - + bfd_boolean local_exec = (bfd_link_executable (info) + && SYMBOL_REFERENCES_LOCAL (info, h)); unsigned int r_type = ELFNN_R_TYPE (rel->r_info); unsigned long insn; bfd_vma sym_size = 0; @@ -7842,7 +7837,7 @@ elfNN_aarch64_tls_relax (bfd *input_bfd, struct bfd_link_info *info, BFD_ASSERT (globals && input_bfd && contents && rel); - if (is_local || !bfd_link_pic (info)) + if (local_exec) { if (h != NULL) sym_size = h->size; @@ -7860,7 +7855,7 @@ elfNN_aarch64_tls_relax (bfd *input_bfd, struct bfd_link_info *info, switch (elfNN_aarch64_bfd_reloc_from_type (input_bfd, r_type)) { case BFD_RELOC_MORELLO_TLSDESC_ADR_PAGE20: - if (is_local || !bfd_link_pic (info)) + if (local_exec) { /* GD->LE relaxation: nop => movz x1, objsize_hi16 @@ -7880,7 +7875,7 @@ elfNN_aarch64_tls_relax (bfd *input_bfd, struct bfd_link_info *info, } case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21: case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21: - if (is_local) + if (local_exec) { /* GD->LE relaxation: adrp x0, :tlsgd:var => movz R0, :tprel_g1:var @@ -7909,7 +7904,7 @@ elfNN_aarch64_tls_relax (bfd *input_bfd, struct bfd_link_info *info, break; case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19: - if (is_local) + if (local_exec) { /* Tiny TLSDESC->LE relaxation: ldr x1, :tlsdesc:var => movz R0, #:tprel_g1:var @@ -7951,7 +7946,7 @@ elfNN_aarch64_tls_relax (bfd *input_bfd, struct bfd_link_info *info, } case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21: - if (is_local) + if (local_exec) { /* Tiny GD->LE relaxation: adr x0, :tlsgd:var => mrs x1, tpidr_el0 @@ -8003,7 +7998,7 @@ elfNN_aarch64_tls_relax (bfd *input_bfd, struct bfd_link_info *info, BFD_ASSERT (rel->r_offset + 12 == rel[2].r_offset); BFD_ASSERT (ELFNN_R_TYPE (rel[2].r_info) == AARCH64_R (CALL26)); - if (is_local) + if (local_exec) { /* Large GD->LE relaxation: movz x0, #:tlsgd_g1:var => movz x0, #:tprel_g2:var, lsl #32 @@ -8047,7 +8042,7 @@ elfNN_aarch64_tls_relax (bfd *input_bfd, struct bfd_link_info *info, return bfd_reloc_continue; case BFD_RELOC_MORELLO_TLSDESC_LD128_LO12: - if (is_local || !bfd_link_pic (info)) + if (local_exec) { /* GD->LE relaxation: ldr xd, [x0, #:tlsdesc_lo12:var] => movk x0, :tprel_g0_nc:var */ @@ -8060,7 +8055,7 @@ elfNN_aarch64_tls_relax (bfd *input_bfd, struct bfd_link_info *info, return bfd_reloc_continue; } case BFD_RELOC_AARCH64_TLSDESC_LDNN_LO12_NC: - if (is_local) + if (local_exec) { /* GD->LE relaxation: ldr xd, [x0, #:tlsdesc_lo12:var] => movk x0, :tprel_g0_nc:var @@ -8081,7 +8076,7 @@ elfNN_aarch64_tls_relax (bfd *input_bfd, struct bfd_link_info *info, } case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC: - if (is_local) + if (local_exec) { /* GD->LE relaxation add x0, #:tlsgd_lo12:var => movk R0, :tprel_g0_nc:var @@ -8126,7 +8121,7 @@ elfNN_aarch64_tls_relax (bfd *input_bfd, struct bfd_link_info *info, case BFD_RELOC_MORELLO_TLSDESC_CALL: /* GD->LE relaxation: blr cd => add c0, c2, x0 */ - if (is_local || !bfd_link_pic (info)) + if (local_exec) { bfd_putl32 (0xc2a06040, contents + rel->r_offset); return bfd_reloc_ok; @@ -8137,7 +8132,7 @@ elfNN_aarch64_tls_relax (bfd *input_bfd, struct bfd_link_info *info, case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12: /* GD->LE relaxation: ldr cd, [c0, #:tlsdesc_lo12:var] => movk x1, objsize_lo16 */ - if ((is_local || !bfd_link_pic (info)) + if (local_exec && ELFNN_R_TYPE (rel[1].r_info) == MORELLO_R (TLSDESC_CALL)) { bfd_putl32 (BUILD_MOVK(1, sym_size), contents + rel->r_offset); @@ -8156,7 +8151,7 @@ set_nop: return bfd_reloc_ok; case BFD_RELOC_AARCH64_TLSDESC_LDR: - if (is_local) + if (local_exec) { /* GD->LE relaxation: ldr xd, [gp, xn] => movk R0, #:tprel_g0_nc:var @@ -8183,12 +8178,12 @@ set_nop: movk xd, #:tlsdesc_off_g0_nc:var => movk Rd, #:gottprel_g0_nc:var Where R is x for lp64 mode, and w for ILP32 mode. */ - if (is_local) + if (local_exec) bfd_putl32 (ldr_hw_R0, contents + rel->r_offset); return bfd_reloc_continue; case BFD_RELOC_AARCH64_TLSDESC_OFF_G1: - if (is_local) + if (local_exec) { /* GD->LE relaxation: movz xd, #:tlsdesc_off_g1:var => movz R0, #:tprel_g2:var, lsl #32 @@ -8213,7 +8208,7 @@ set_nop: adrp xd, :gottprel:var => movz Rd, :tprel_g1:var Where R is x for lp64 mode, and w for ILP32 mode. */ - if (is_local) + if (local_exec) { insn = bfd_getl32 (contents + rel->r_offset); bfd_putl32 (movz_R0 | (insn & 0x1f), contents + rel->r_offset); @@ -8228,7 +8223,7 @@ set_nop: ldr xd, [xm, #:gottprel_lo12:var] => movk Rd, :tprel_g0_nc:var Where R is x for lp64 mode, and w for ILP32 mode. */ - if (is_local) + if (local_exec) { insn = bfd_getl32 (contents + rel->r_offset); bfd_putl32 (movk_R0 | (insn & 0x1f), contents + rel->r_offset); @@ -8241,7 +8236,7 @@ set_nop: bl __tls_get_addr => add R0, R0, TCB_SIZE Where R is x for lp64 mode, and w for ilp32 mode. */ - if (is_local) + if (local_exec) { BFD_ASSERT (rel->r_offset + 4 == rel[1].r_offset); BFD_ASSERT (ELFNN_R_TYPE (rel[1].r_info) == AARCH64_R (CALL26)); @@ -8258,7 +8253,7 @@ set_nop: /* LD->LE relaxation (small): adrp x0, :tlsldm:x => mrs x0, tpidr_el0 */ - if (is_local) + if (local_exec) { bfd_putl32 (0xd53bd040, contents + rel->r_offset); return bfd_reloc_ok; @@ -8271,7 +8266,7 @@ set_nop: bl __tls_get_addr => nop Where R is x for lp64 mode, and w for ilp32 mode. */ - if (is_local) + if (local_exec) { BFD_ASSERT (rel->r_offset + 4 == rel[1].r_offset); BFD_ASSERT (ELFNN_R_TYPE (rel[1].r_info) == AARCH64_R (CALL26)); diff --git a/ld/testsuite/ld-aarch64/aarch64-elf.exp b/ld/testsuite/ld-aarch64/aarch64-elf.exp index 5af3bbfa84151cbfca25dd5580407def9387fba0..38ee991e20d048a0359bf01f403e8329003c0aea 100644 --- a/ld/testsuite/ld-aarch64/aarch64-elf.exp +++ b/ld/testsuite/ld-aarch64/aarch64-elf.exp @@ -375,17 +375,8 @@ run_dump_test "tls-relax-gd-le-ilp32" run_dump_test "tls-relax-gdesc-le" run_dump_test "tls-relax-gdesc-le-now" run_dump_test "tls-relax-gdesc-le-ilp32" -run_dump_test "tls-relax-gd-ie" -run_dump_test "tls-relax-gd-ie-ilp32" -run_dump_test_lp64 "tls-relax-large-gd-ie" -run_dump_test_lp64 "tls-relax-large-gd-ie-be" run_dump_test_lp64 "tls-relax-large-gd-le" run_dump_test_lp64 "tls-relax-large-gd-le-be" -run_dump_test_lp64 "tls-relax-large-desc-ie" -run_dump_test_lp64 "tls-relax-large-desc-ie-be" -run_dump_test_lp64 "tls-relax-large-desc-le" -run_dump_test_lp64 "tls-relax-large-desc-le-be" -run_dump_test "tls-relax-gdesc-ie" run_dump_test "tls-relax-ie-le" run_dump_test "tls-relax-ie-le-ilp32" run_dump_test "tls-relax-ld-le-small" @@ -394,7 +385,6 @@ run_dump_test "tls-relax-ld-le-tiny" run_dump_test "tls-relax-ld-le-tiny-ilp32" run_dump_test "tls-desc-ie" run_dump_test "tls-desc-ie-ilp32" -run_dump_test "tls-relax-gdesc-ie-2" run_dump_test "tls-relax-gdesc-le-2" run_dump_test "tls-relax-gdesc-le-2-ilp32" run_dump_test "tls-relax-ie-le-2" @@ -402,13 +392,9 @@ run_dump_test "tls-relax-ie-le-2-ilp32" run_dump_test "tls-relax-ie-le-3" run_dump_test "tls-relax-ie-le-3-ilp32" run_dump_test "tls-tiny-gd" -run_dump_test "tls-tiny-gd-ie" -run_dump_test "tls-tiny-gd-ie-ilp32" run_dump_test "tls-tiny-gd-le" run_dump_test "tls-tiny-gd-le-ilp32" run_dump_test "tls-tiny-desc" -run_dump_test "tls-tiny-desc-ie" -run_dump_test "tls-tiny-desc-ie-ilp32" run_dump_test "tls-tiny-desc-le" run_dump_test "tls-tiny-desc-le-ilp32" run_dump_test "tls-tiny-ie" @@ -433,6 +419,31 @@ run_dump_test "protected-data" run_dump_test_lp64 "pr22764" run_dump_test_lp64 "pr20402" +if {[check_shared_lib_support] + && [ld_assemble $as $srcdir/$subdir/tls-sharedlib.s tmpdir/tls-sharedlib.o] + && [ld_link $ld tmpdir/tls-sharedlib.so "-shared tmpdir/tls-sharedlib.o"] } { + run_dump_test "tls-relax-gd-ie" + run_dump_test_lp64 "tls-relax-large-gd-ie" + run_dump_test_lp64 "tls-relax-large-gd-ie-be" + run_dump_test_lp64 "tls-relax-large-desc-ie" + run_dump_test_lp64 "tls-relax-large-desc-ie-be" + run_dump_test_lp64 "tls-relax-large-desc-le" + run_dump_test_lp64 "tls-relax-large-desc-le-be" + run_dump_test "tls-relax-gdesc-ie" + run_dump_test "tls-relax-gdesc-ie-2" + run_dump_test "tls-tiny-gd-ie" + run_dump_test "tls-tiny-desc-ie" +} +if {[check_shared_lib_support] + && [ld_assemble_flags $as -mabi=ilp32 $srcdir/$subdir/tls-sharedlib.s tmpdir/tls-sharedlib.o] + && [ld_link $ld tmpdir/tls-sharedlib-ilp32.so "-shared tmpdir/tls-sharedlib.o -m [aarch64_choose_ilp32_emul]"] } { + run_dump_test "tls-relax-gd-ie-ilp32" + run_dump_test "tls-tiny-gd-ie-ilp32" + run_dump_test "tls-tiny-desc-ie-ilp32" +} +run_dump_test "tls-relax-gd-ie-2" +run_dump_test "tls-relax-ie-le-4" + # ifunc tests run_dump_test "ifunc-1" run_dump_test "ifunc-1-local" diff --git a/ld/testsuite/ld-aarch64/relocs-ilp32.ld b/ld/testsuite/ld-aarch64/relocs-ilp32.ld index 7174aff236f189a1ae5caa94ecaf27c7ddb171b5..4ddba9141209a48c1342c4ffaf65b327d91873a8 100644 --- a/ld/testsuite/ld-aarch64/relocs-ilp32.ld +++ b/ld/testsuite/ld-aarch64/relocs-ilp32.ld @@ -16,4 +16,8 @@ SECTIONS . = 0x12340000; .far : { *(.far) } .ARM.attributes 0 : { *(.ARM.atttributes) } + /* Providing a .data section triggers a non-executable segment to be + generated, which gives somewhere else for the linker to put the TLS + segment without creating a RWX permissioned one. */ + .data : { *(.data) } } diff --git a/ld/testsuite/ld-aarch64/relocs.ld b/ld/testsuite/ld-aarch64/relocs.ld index f42176e64d30daa9949c0679ff3b0a931de46dfd..77adac8b46e01b488e68405b1291335a2dfa29fc 100644 --- a/ld/testsuite/ld-aarch64/relocs.ld +++ b/ld/testsuite/ld-aarch64/relocs.ld @@ -16,4 +16,8 @@ SECTIONS . = 0x12340000; .far : { *(.far) } .ARM.attributes 0 : { *(.ARM.atttributes) } + /* Providing a .data section triggers a non-executable segment to be + generated, which gives somewhere else for the linker to put the TLS + segment without creating a RWX permissioned one. */ + .data : { *(.data) } } diff --git a/ld/testsuite/ld-aarch64/tls-relax-all-ilp32.d b/ld/testsuite/ld-aarch64/tls-relax-all-ilp32.d index 1cb4ef4261307c13139707ad27b8e85bbe11b0a9..62faed4b73aac484119ed18dbc7f588f6ec8c794 100644 --- a/ld/testsuite/ld-aarch64/tls-relax-all-ilp32.d +++ b/ld/testsuite/ld-aarch64/tls-relax-all-ilp32.d @@ -5,8 +5,8 @@ #... +10000: a9bf7bfd stp x29, x30, \[sp, #-16\]! +10004: 910003fd mov x29, sp - +10008: 90000080 adrp x0, 20000 <_GLOBAL_OFFSET_TABLE_> - +1000c: b9400400 ldr w0, \[x0, #4\] + +10008: 52a00000 movz w0, #0x0, lsl #16 + +1000c: 72800100 movk w0, #0x8 +10010: d503201f nop +10014: d503201f nop +10018: d53bd041 mrs x1, tpidr_el0 @@ -20,8 +20,8 @@ +10038: 8b000040 add x0, x2, x0 +1003c: b9400000 ldr w0, \[x0\] +10040: 0b000021 add w1, w1, w0 - +10044: 90000080 adrp x0, 20000 <_GLOBAL_OFFSET_TABLE_> - +10048: b9400800 ldr w0, \[x0, #8\] + +10044: 52a00000 movz w0, #0x0, lsl #16 + +10048: 72800200 movk w0, #0x10 +1004c: d53bd041 mrs x1, tpidr_el0 +10050: 0b000020 add w0, w1, w0 +10054: b9400000 ldr w0, \[x0\] diff --git a/ld/testsuite/ld-aarch64/tls-relax-all.d b/ld/testsuite/ld-aarch64/tls-relax-all.d index 59421864f9558050bf1d2ae1cab794bf54ac30df..1262a99a6a0debb22256903a25e9075f1666543b 100644 --- a/ld/testsuite/ld-aarch64/tls-relax-all.d +++ b/ld/testsuite/ld-aarch64/tls-relax-all.d @@ -4,8 +4,8 @@ #... +10000: a9bf7bfd stp x29, x30, \[sp, #-16\]! +10004: 910003fd mov x29, sp - +10008: 90000080 adrp x0, 20000 <_GLOBAL_OFFSET_TABLE_> - +1000c: f9400400 ldr x0, \[x0, #8\] + +10008: d2a00000 movz x0, #0x0, lsl #16 + +1000c: f2800200 movk x0, #0x10 +10010: d503201f nop +10014: d503201f nop +10018: d53bd041 mrs x1, tpidr_el0 @@ -19,8 +19,8 @@ +10038: 8b000040 add x0, x2, x0 +1003c: b9400000 ldr w0, \[x0\] +10040: 0b000021 add w1, w1, w0 - +10044: 90000080 adrp x0, 20000 <_GLOBAL_OFFSET_TABLE_> - +10048: f9400800 ldr x0, \[x0, #16\] + +10044: d2a00000 movz x0, #0x0, lsl #16 + +10048: f2800300 movk x0, #0x18 +1004c: d53bd041 mrs x1, tpidr_el0 +10050: 8b000020 add x0, x1, x0 +10054: b9400000 ldr w0, \[x0\] diff --git a/ld/testsuite/ld-aarch64/tls-relax-gd-ie-2.d b/ld/testsuite/ld-aarch64/tls-relax-gd-ie-2.d new file mode 100644 index 0000000000000000000000000000000000000000..bb5713e3726e7b5b363b497fb6784a1b705265f5 --- /dev/null +++ b/ld/testsuite/ld-aarch64/tls-relax-gd-ie-2.d @@ -0,0 +1,26 @@ +# The linker recognises that if we have one IE access to a TLS symbol then all +# accesses to that symbol could be IE. Here we are also interested to check +# the linker does not also decide that a second access to that symbol could be +# LE. +#ld: -shared +#objdump: -dr + +.*: file format .* + + +Disassembly of section \.text: + +[0-9a-f]+ <foo>: + +[0-9a-f]+: d2800000 mov x0, #0x0 // #0 + +[0-9a-f]+: d53bd041 mrs x1, tpidr_el0 + +[0-9a-f]+: .* adrp x0, .* + +[0-9a-f]+: .* ldr x0, \[x0, #.*\] + +[0-9a-f]+: b8606820 ldr w0, \[x1, x0\] + +[0-9a-f]+: d53bd041 mrs x1, tpidr_el0 + +[0-9a-f]+: 910003fd mov x29, sp + +[0-9a-f]+: .* adrp x0, .* + +[0-9a-f]+: .* ldr x0, \[x0, #.*\] + +[0-9a-f]+: d503201f nop + +[0-9a-f]+: d503201f nop + +[0-9a-f]+: b8606820 ldr w0, \[x1, x0\] + +[0-9a-f]+: d65f03c0 ret diff --git a/ld/testsuite/ld-aarch64/tls-relax-gd-ie-2.s b/ld/testsuite/ld-aarch64/tls-relax-gd-ie-2.s new file mode 100644 index 0000000000000000000000000000000000000000..79bdc84f81326d375534a1f25780825c09c0d724 --- /dev/null +++ b/ld/testsuite/ld-aarch64/tls-relax-gd-ie-2.s @@ -0,0 +1,35 @@ + # N.b. a local symbol `g`. + .section .tbss,"awT",@nobits + .align 2 + .type y, %object + .size y, 4 +y: + .zero 4 + + + + + .text + .global foo + .type foo, @function +foo: + # Access the local symbol with an IE access. + mov x0, 0 + mrs x1, tpidr_el0 + adrp x0, :gottprel:y + ldr x0, [x0, #:gottprel_lo12:y] + ldr w0, [x1, x0] + + # Also access the same symbol with a General Dynamic access. + # The linker should be able to recognise that if we're already + # accessing this symbol with an Initial Exec access then this General + # Dynamic access could be relaxed to an Initial Exec one too. + mrs x1, tpidr_el0 + mov x29, sp + adrp x0, :tlsdesc:y + ldr x2, [x0, #:tlsdesc_lo12:y] + add x0, x0, :tlsdesc_lo12:y + .tlsdesccall y + blr x2 + ldr w0, [x1, x0] + ret diff --git a/ld/testsuite/ld-aarch64/tls-relax-gd-ie-ilp32.d b/ld/testsuite/ld-aarch64/tls-relax-gd-ie-ilp32.d index ab08c6161b9330110a9ffbb33eb6d44b0a8e8ac7..340206a9e2bbd37534eb3a1fed79e6386480aed3 100644 --- a/ld/testsuite/ld-aarch64/tls-relax-gd-ie-ilp32.d +++ b/ld/testsuite/ld-aarch64/tls-relax-gd-ie-ilp32.d @@ -1,6 +1,6 @@ #source: tls-relax-gd-ie.s #as: -mabi=ilp32 -#ld: -m [aarch64_choose_ilp32_emul] -T relocs-ilp32.ld -e0 +#ld: -m [aarch64_choose_ilp32_emul] -T relocs-ilp32.ld -e0 tmpdir/tls-sharedlib-ilp32.so #objdump: -dr #... +10000: 90000080 adrp x0, 20000 <_GLOBAL_OFFSET_TABLE_> diff --git a/ld/testsuite/ld-aarch64/tls-relax-gd-ie.d b/ld/testsuite/ld-aarch64/tls-relax-gd-ie.d index f80bb9077705d83e793fcdd6b45169ac82a24aa9..0c03290e0a9cca61baab061e0b24475f9a8f00ab 100644 --- a/ld/testsuite/ld-aarch64/tls-relax-gd-ie.d +++ b/ld/testsuite/ld-aarch64/tls-relax-gd-ie.d @@ -1,5 +1,5 @@ #source: tls-relax-gd-ie.s -#ld: -T relocs.ld -e0 +#ld: -T relocs.ld -e0 tmpdir/tls-sharedlib.so #objdump: -dr #... +10000: 90000080 adrp x0, 20000 <_GLOBAL_OFFSET_TABLE_> diff --git a/ld/testsuite/ld-aarch64/tls-relax-gd-ie.s b/ld/testsuite/ld-aarch64/tls-relax-gd-ie.s index 88c7eec73e43afb680a6c1c9051bf5485491fa1e..afe076c8c8203ee547e84ccab544b67e388279d3 100644 --- a/ld/testsuite/ld-aarch64/tls-relax-gd-ie.s +++ b/ld/testsuite/ld-aarch64/tls-relax-gd-ie.s @@ -1,7 +1,3 @@ - .global var - .section .tdata,"awT",%progbits -var: - .word 2 .text adrp x0, :tlsgd:var add x0, x0, :tlsgd_lo12:var diff --git a/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie-2.d b/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie-2.d index 2b8e346fc66c79c3d992714da7a876dc83c0b5ee..f13263f201ff781b0c8c41f468c069ee71c4fd61 100644 --- a/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie-2.d +++ b/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie-2.d @@ -1,5 +1,5 @@ #source: tls-relax-gdesc-ie-2.s -#ld: -T relocs.ld -e0 +#ld: -T relocs.ld -e0 tmpdir/tls-sharedlib.so #objdump: -dr #... +10000: 90000080 adrp x0, 20000 <_GLOBAL_OFFSET_TABLE_> diff --git a/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie-2.s b/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie-2.s index 790b6c6eb8bb4b9c2efa0688f46a5413d8231f78..f7be57c320716d6c56559d2ebfa181a2944bdb88 100644 --- a/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie-2.s +++ b/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie-2.s @@ -1,9 +1,5 @@ // Test TLS Desc to TLS IE relaxation when instructions are not consecutive. - .global var - .section .tdata -var: - .word 2 .text adrp x0, :tlsdesc:var nop @@ -20,5 +16,4 @@ var: mrs x1, tpidr_el0 add x0, x1, x0 ldr w0, [x0] - .global var .section .tdata diff --git a/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.d b/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.d index 86277f82565c401aa6d2b4b365e2c9c8bc8ccfe6..1ace84858a32e1ef0336cf24f7017a55ccbb611e 100644 --- a/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.d +++ b/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.d @@ -1,5 +1,5 @@ #source: tls-relax-gdesc-ie.s -#ld: -T relocs.ld -e0 +#ld: -T relocs.ld -e0 tmpdir/tls-sharedlib.so #objdump: -dr #... +10000: 90000080 adrp x0, 20000 <_GLOBAL_OFFSET_TABLE_> diff --git a/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.s b/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.s index 38b372132f49c926be8d6527bce9d203b794a4b5..089d36c9cc8a9f4dd9f6cfe71996bdbdd9b68502 100644 --- a/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.s +++ b/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.s @@ -1,7 +1,3 @@ - .global var - .section .tdata -var: - .word 2 .text adrp x0, :tlsdesc:var ldr x17, [x0, #:tlsdesc_lo12:var] diff --git a/ld/testsuite/ld-aarch64/tls-relax-ie-le-4.d b/ld/testsuite/ld-aarch64/tls-relax-ie-le-4.d new file mode 100644 index 0000000000000000000000000000000000000000..e2bc5f1530440d19077c455db5783ef10da24bf2 --- /dev/null +++ b/ld/testsuite/ld-aarch64/tls-relax-ie-le-4.d @@ -0,0 +1,20 @@ +# We already test that we relax an access to a local symbol, this testcase +# checks that we relax an access to a global-binding symbol if the static linker +# knows that the symbol will resolve to the executable local value. +# +# The access should be relaxed to a LE access. +#ld: +#objdump: -d + +.*: file format .* + + +Disassembly of section \.text: + +[0-9a-f]+ <_start>: + +[0-9a-f]+: d2800000 mov x0, #0x0 // #0 + +[0-9a-f]+: d53bd041 mrs x1, tpidr_el0 + +[0-9a-f]+: d2a00000 movz x0, #0x0, lsl #16 + +[0-9a-f]+: f2800200 movk x0, #0x10 + +[0-9a-f]+: b8606820 ldr w0, \[x1, x0\] + +[0-9a-f]+: d65f03c0 ret diff --git a/ld/testsuite/ld-aarch64/tls-relax-ie-le-4.s b/ld/testsuite/ld-aarch64/tls-relax-ie-le-4.s new file mode 100644 index 0000000000000000000000000000000000000000..e151cd4efd6cc729d220ceea5f318ecd3a8ed3d8 --- /dev/null +++ b/ld/testsuite/ld-aarch64/tls-relax-ie-le-4.s @@ -0,0 +1,22 @@ +# Test TLS IE to TLS LE relaxation for global symbols. + .section .tbss,"awT",@nobits + .global x + .align 2 + .type x, %object + .size x, 4 +x: + .zero 4 + + + + .text + .global _start + .type _start, @function +_start: + mov x0, 0 + mrs x1, tpidr_el0 + adrp x0, :gottprel:x + ldr x0, [x0, #:gottprel_lo12:x] + ldr w0, [x1, x0] + ret + diff --git a/ld/testsuite/ld-aarch64/tls-relax-large-desc-ie.d b/ld/testsuite/ld-aarch64/tls-relax-large-desc-ie.d index 21ad5e5a18c265e5e095b2053752a578d689d411..cb546ad74e6da35e7d3cd4f56ba62af52afebc22 100644 --- a/ld/testsuite/ld-aarch64/tls-relax-large-desc-ie.d +++ b/ld/testsuite/ld-aarch64/tls-relax-large-desc-ie.d @@ -1,5 +1,5 @@ #source: tls-relax-large-desc-ie.s -#ld: -T relocs.ld -e0 +#ld: -T relocs.ld -e0 tmpdir/tls-sharedlib.so #notarget: aarch64_be-*-* #objdump: -dr #... diff --git a/ld/testsuite/ld-aarch64/tls-relax-large-desc-ie.s b/ld/testsuite/ld-aarch64/tls-relax-large-desc-ie.s index a4d1e00086ad3ed3818eb73b4aba606cb0de6cf7..98dc2a571d5836b60f05cb9daf47b385456a3ee2 100644 --- a/ld/testsuite/ld-aarch64/tls-relax-large-desc-ie.s +++ b/ld/testsuite/ld-aarch64/tls-relax-large-desc-ie.s @@ -1,8 +1,3 @@ - .global var - .section .tdata,"awT",%progbits -var: - .word 2 - .text test: ldr x1, .Lgot diff --git a/ld/testsuite/ld-aarch64/tls-relax-large-gd-ie.d b/ld/testsuite/ld-aarch64/tls-relax-large-gd-ie.d index 2b398dbb9c6ce48f48f258e3ed337dcd383af82c..740178d46105483fa4176b1a4c77ebac459ef846 100644 --- a/ld/testsuite/ld-aarch64/tls-relax-large-gd-ie.d +++ b/ld/testsuite/ld-aarch64/tls-relax-large-gd-ie.d @@ -1,5 +1,5 @@ #source: tls-relax-large-gd-ie.s -#ld: -T relocs.ld -e0 +#ld: -T relocs.ld -e0 tmpdir/tls-sharedlib.so #notarget: aarch64_be-*-* #objdump: -dr #... diff --git a/ld/testsuite/ld-aarch64/tls-relax-large-gd-ie.s b/ld/testsuite/ld-aarch64/tls-relax-large-gd-ie.s index 8e0310d6b3f8caecdbfc2bdd3f310b6ee3942d80..d35aace776ee0bc327cfa1cf258c8ce687865d7a 100644 --- a/ld/testsuite/ld-aarch64/tls-relax-large-gd-ie.s +++ b/ld/testsuite/ld-aarch64/tls-relax-large-gd-ie.s @@ -1,8 +1,3 @@ - .global var - .section .tdata,"awT",%progbits -var: - .word 2 - .text test: ldr x1, .Lgot diff --git a/ld/testsuite/ld-aarch64/tls-sharedlib.s b/ld/testsuite/ld-aarch64/tls-sharedlib.s new file mode 100644 index 0000000000000000000000000000000000000000..8838b9f23484ac6c0535c43256818050fbf3a4fd --- /dev/null +++ b/ld/testsuite/ld-aarch64/tls-sharedlib.s @@ -0,0 +1,4 @@ + .global var + .section .tdata,"awT",@progbits +var: + .word 2 diff --git a/ld/testsuite/ld-aarch64/tls-tiny-desc-ie-ilp32.d b/ld/testsuite/ld-aarch64/tls-tiny-desc-ie-ilp32.d index ebbaf854baa9548503d0eeac351ab3ee6e330183..3dffa1b85e6376fd72970ba79ecf8d42640173ae 100644 --- a/ld/testsuite/ld-aarch64/tls-tiny-desc-ie-ilp32.d +++ b/ld/testsuite/ld-aarch64/tls-tiny-desc-ie-ilp32.d @@ -1,12 +1,12 @@ #source: tls-tiny-desc-ie.s #as: -mabi=ilp32 -#ld: -m [aarch64_choose_ilp32_emul] -T relocs-ilp32.ld -e0 +#ld: -m [aarch64_choose_ilp32_emul] -T relocs-ilp32.ld -e0 tmpdir/tls-sharedlib-ilp32.so #objdump: -dr #... Disassembly of section .text: 00010000 \<test\>: - +10000: 18080020 ldr w0, 20004 \<_GLOBAL_OFFSET_TABLE_\+0x4\> + +10000: 18080020 ldr w0, 20004 \<var\> +10004: d503201f nop +10008: d503201f nop diff --git a/ld/testsuite/ld-aarch64/tls-tiny-desc-ie.d b/ld/testsuite/ld-aarch64/tls-tiny-desc-ie.d index 0088539d6bfae0bdfc70c86afeaf7f1d16305d12..e759ae94576ccca484a9690d1334032f97df6fd6 100644 --- a/ld/testsuite/ld-aarch64/tls-tiny-desc-ie.d +++ b/ld/testsuite/ld-aarch64/tls-tiny-desc-ie.d @@ -1,11 +1,11 @@ #source: tls-tiny-desc-ie.s -#ld: -T relocs.ld -e0 +#ld: -T relocs.ld -e0 tmpdir/tls-sharedlib.so #objdump: -dr #... Disassembly of section .text: 0000000000010000 \<test\>: - +10000: 58080040 ldr x0, 20008 \<_GLOBAL_OFFSET_TABLE_\+0x8\> + +10000: 58080040 ldr x0, 20008 \<var\> +10004: d503201f nop +10008: d503201f nop diff --git a/ld/testsuite/ld-aarch64/tls-tiny-desc-ie.s b/ld/testsuite/ld-aarch64/tls-tiny-desc-ie.s index 520cd4e85b29f8c3acc912d2d31b902b91ee337e..fcc970f6d8f46b7c57724b55c857dcee77bc0722 100644 --- a/ld/testsuite/ld-aarch64/tls-tiny-desc-ie.s +++ b/ld/testsuite/ld-aarch64/tls-tiny-desc-ie.s @@ -1,12 +1,3 @@ - .global var - - .section .tbss,"awT",%nobits - .align 2 - .type var, %object - .size var, 4 -var: - .zero 4 - .text test: ldr x1, :tlsdesc:var diff --git a/ld/testsuite/ld-aarch64/tls-tiny-gd-ie-ilp32.d b/ld/testsuite/ld-aarch64/tls-tiny-gd-ie-ilp32.d index 1ea61103b47ba1a23703be914da5f5f1008a9cb1..6317152eb1ecc8830d8a0b736276c4ef19301d58 100644 --- a/ld/testsuite/ld-aarch64/tls-tiny-gd-ie-ilp32.d +++ b/ld/testsuite/ld-aarch64/tls-tiny-gd-ie-ilp32.d @@ -1,12 +1,12 @@ #source: tls-tiny-gd-ie.s #as: -mabi=ilp32 -#ld: -m [aarch64_choose_ilp32_emul] -T relocs-ilp32.ld -e0 +#ld: -m [aarch64_choose_ilp32_emul] -T relocs-ilp32.ld -e0 tmpdir/tls-sharedlib-ilp32.so #objdump: -dr #... Disassembly of section .text: 00010000 \<test\>: - +10000: 18080020 ldr w0, 20004 \<_GLOBAL_OFFSET_TABLE_\+0x4\> + +10000: 18080020 ldr w0, 20004 \<var\> +10004: d53bd041 mrs x1, tpidr_el0 +10008: 0b000020 add w0, w1, w0 diff --git a/ld/testsuite/ld-aarch64/tls-tiny-gd-ie.d b/ld/testsuite/ld-aarch64/tls-tiny-gd-ie.d index 629d90c942d34845e700b935ef2701d06235b7dd..66b996e6f4abc279d96be510956eff0c606ab240 100644 --- a/ld/testsuite/ld-aarch64/tls-tiny-gd-ie.d +++ b/ld/testsuite/ld-aarch64/tls-tiny-gd-ie.d @@ -1,11 +1,11 @@ #source: tls-tiny-gd-ie.s -#ld: -T relocs.ld -e0 +#ld: -T relocs.ld -e0 tmpdir/tls-sharedlib.so #objdump: -dr #... Disassembly of section .text: 0000000000010000 \<test\>: - +10000: 58080040 ldr x0, 20008 \<_GLOBAL_OFFSET_TABLE_\+0x8\> + +10000: 58080040 ldr x0, 20008 \<var\> +10004: d53bd041 mrs x1, tpidr_el0 +10008: 8b000020 add x0, x1, x0 diff --git a/ld/testsuite/ld-aarch64/tls-tiny-gd-ie.s b/ld/testsuite/ld-aarch64/tls-tiny-gd-ie.s index 4dc7e66bbdb7d7c01754aebcdaf4b1328667e143..3ae4a0cc9fe1329140c60ed9424b80e8b4669da3 100644 --- a/ld/testsuite/ld-aarch64/tls-tiny-gd-ie.s +++ b/ld/testsuite/ld-aarch64/tls-tiny-gd-ie.s @@ -1,12 +1,3 @@ - .global var - - .section .tbss,"awT",%nobits - .align 2 - .type var, %object - .size var, 4 -var: - .zero 4 - .text test: adr x0, :tlsgd:var

1 year, 9 months

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[To be committed]: Standardise check for static PDE

by Matthew Malcomson

We have hit multiple problems checking for a static non-PIE binary using incorrect conditions. In looking into a TLS relaxation that should not have happened we found another. To help avoid this problem in the future (and to make reading the code a lot easier for someone who isn't familiar with the BFD linker flags) we now perform the check for a static PDE with a macro called `static_pde`. N.b. this macro can only be used after we've created any needed dynamic sections. That happens when loading symbols, which is very early on and hence before any of the places we want to use this macro. However it's still good to note it's not always a valid check. ############### Attachment also inlined for ease of reply ############### diff --git a/bfd/elfnn-aarch64.c b/bfd/elfnn-aarch64.c index 1b6e80aa20982c294780cc20cd49c1702549a47c..a0898f9e7b9e44ae609bbc0a6eae5eaa830771e2 100644 --- a/bfd/elfnn-aarch64.c +++ b/bfd/elfnn-aarch64.c @@ -292,6 +292,17 @@ (((htab)->root.srelplt == NULL) ? 0 \ : (htab)->root.srelplt->reloc_count * GOT_ENTRY_SIZE (htab)) +/* Macro to check for a static non-PIE binary. Checking for this in incorrect + ways is something that has been the cause of a few bugs throughout Morello + development. Making a macro for the check should help make this easier to + check. + N.b. this macro can only be called after symbols have been loaded by the + generic linker. In practice this is not much of a restriction, since the + check_relocs, size_dynamic_sections, and relocate_section hooks are all done + after that point. */ +#define static_pde(info) (!elf_hash_table (info)->dynamic_sections_created \ + && bfd_link_executable (info)) + /* The only time that we want the value of a symbol but do not want a relocation for it in Morello is when that symbol is undefined weak. In this case we just need the zero capability and there's no point emitting a @@ -7438,7 +7449,7 @@ elfNN_aarch64_final_link_relocate (reloc_howto_type *howto, done so that we can mark that section with __rela_dyn_{start,end} symbols for the runtime to find and initialise relocations with. */ - if (bfd_link_executable (info) && !is_dynamic) + if (static_pde (info)) s = globals->srelcaps; outrel.r_addend = signed_addend; @@ -9146,8 +9157,7 @@ aarch64_elf_init_got_section (bfd *abfd, struct bfd_link_info *info) } /* Track capability initialisation for static non-PIE binaries. */ - if (bfd_link_executable (info) && !globals->root.dynamic_sections_created - && globals->srelcaps == NULL) + if (static_pde (info) && globals->srelcaps == NULL) globals->srelcaps = globals->root.srelgot; if (globals->root.igotplt != NULL) @@ -10288,22 +10298,16 @@ elfNN_aarch64_allocate_dynrelocs (struct elf_link_hash_entry *h, void *inf) symbol that we know will not be resolved to anything by the runtime do not need a relocation. */ } - else if (dyn) - { - /* Any capability relocations required in a dynamic binary - should go in the srelgot. N.b. many capability relocations - would be caught by the first clause in this if chain. */ - htab->root.srelgot->size += RELOC_SIZE (htab); - } - else if (bfd_link_executable (info)) - { - /* If we have a capability relocation that is not handled by the - case above then this must be a statically linked executable. - We want capability relocations in a statically linked - executable to go in the srelcaps section. */ - BFD_ASSERT (!bfd_link_pic (info) && !dyn); - htab->srelcaps->size += RELOC_SIZE (htab); - } + else if (!static_pde (info)) + /* Any capability relocations required in something other than a + static PDE should go in the srelgot. N.b. many capability + relocations would be caught by the first clause in this if + chain. */ + htab->root.srelgot->size += RELOC_SIZE (htab); + else + /* We want capability relocations in a statically linked + PDE to go in the srelcaps section. */ + htab->srelcaps->size += RELOC_SIZE (htab); } else { @@ -10646,10 +10650,8 @@ elfNN_aarch64_size_dynamic_sections (bfd *output_bfd, || got_type & GOT_NORMAL) htab->root.srelgot->size += RELOC_SIZE (htab); } - /* Static binary; put relocs into srelcaps. */ - else if (bfd_link_executable (info) - && !htab->root.dynamic_sections_created - && htab->c64_rel) + /* Static non-PIE; put relocs into srelcaps. */ + else if (static_pde (info) && htab->c64_rel) htab->srelcaps->size += RELOC_SIZE (htab); /* Else capability relocation needs to go into srelgot. */ else if (htab->c64_rel) @@ -10678,8 +10680,7 @@ elfNN_aarch64_size_dynamic_sections (bfd *output_bfd, elfNN_aarch64_allocate_local_ifunc_dynrelocs, info); - if (bfd_link_executable (info) - && !htab->root.dynamic_sections_created + if (static_pde (info) && htab->srelcaps && htab->srelcaps->size > 0) {

1 year, 9 months

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malloc returns null

by Vadim Zaliva

When running baremetal binaries under qemu (as discussed in the other thread), malloc is returning NULL. Is this expected in this configuration? Vadim -- Senior Research Associate Department of Computer Science and Technology University of Cambridge http://zaliva.org/

1 year, 9 months

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running baremetal binaries under qemu

by Vadim Zaliva

I am trying to rung GCC-produced binaries under qemu, with no success. Here is what I did: dummy.c: #include <stdio.h> int main() { fprintf(stderr,"hello world!\n"); } $ ~/morello-gnu/bin/aarch64-none-elf-gcc -march=morello+c64 -mabi=purecap -specs=aem-ve.specs -O0 tests/cheri/dummy.c -o dummy $ file dummy dummy: ELF 64-bit LSB executable, ARM aarch64, version 1 (SYSV), statically linked, with debug_info, not stripped $ ~/cheri/output/morello-sdk/bin/qemu-system-morello -M virt,gic-version=3 -cpu morello -m 2048 -nographic -device virtio-rng-pci -bios dummy At this point, qemu hangs up eating a lot of CPU and has to be killed. Any suggestions on how I can run the binaries? Vadim -- Senior Research Associate Department of Computer Science and Technology University of Cambridge http://zaliva.org/

1 year, 9 months

4
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[To Be Committed]: Neaten up a clause in final_link_relocate

by Matthew Malcomson

Originally this clause included lines checking `!bfd_link_pic && bfd_link_executable`. I left these in to ensure that the new Morello part to the clause did not interfere with the original stock AArch64 part of the clause. Now we have split the condition into multiple if statements for clarity, we can remove the confusing parts of the clause. This clause is to catch any symbols that go in the GOT but would not be otherwise given a relocation by finish_dynamic_symbol. We can express that check better with a modified condition. What we want to do in this clause is to account for all GOT entries which would not get a dynamic relocation otherwise, but need a RELATIVE dynamic relocation for Morello. This is any symbol for which c64_should_not_relocate is false and WILL_CALL_FINISH_DYNAMIC_SYMBOL is false. Changing the clause to only mention these two predicates (plus ensuring that we do not mess around with such relocations when creating a relocatable object file rather than a final binary) explains the purpose of this condition much better. N.b. see the commit message of 8f5baae3d15 for the reasoning for the original decision to not change the conditional. ############### Attachment also inlined for ease of reply ############### diff --git a/bfd/elfnn-aarch64.c b/bfd/elfnn-aarch64.c index bb17f18e498ae3118c70636b8e6318511b9a0ccd..6d45d5d68a3213bf7f22710271a39e1478b745c5 100644 --- a/bfd/elfnn-aarch64.c +++ b/bfd/elfnn-aarch64.c @@ -7276,10 +7276,9 @@ elfNN_aarch64_final_link_relocate (reloc_howto_type *howto, This clause catches the case when we're not relocating for GOT, or when we're relocating an undefined weak symbol. */ } - else if (!bfd_link_pic (info) + else if (!bfd_link_relocatable (info) && !WILL_CALL_FINISH_DYNAMIC_SYMBOL (is_dynamic, bfd_link_pic (info), h) - && bfd_link_executable (info) && !symbol_got_offset_mark_p (input_bfd, h, r_symndx)) { /* This clause is here to catch any c64 entries in the GOT which

1 year, 10 months

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Gnu-morello